SerDes Circuit Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $129,300–$225,300 / yr
Posted: 116 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $177k

$117k $247k

below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $164,500–$229,100 — the blue band above. At the midpoint, this role pays about $177k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SerDes Circuit Design Engineer

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The SerDes Circuit Design Engineer joins the high-speed SerDes team to develop next-generation high-performance wireline transceivers for system-on-chip intellectual property. Working with cross-functional teams, the engineer designs and executes state-of-the-art analog mixed-signal circuits for SerDes PHY, including Rx, CDR, Tx, bias generators, and high-speed clock generation. Key responsibilities involve evaluating circuit topologies for optimal power, performance, and area, creating block-level specifications, and performing transistor-level implementation and behavioral modeling. The role requires expertise in advanced CMOS and FinFet technologies, along with skills in SystemVerilog, Matlab, Python, and VerilogAMS. Candidates must understand Tx/Rx equalization for 64+ Gbps NRZ and PAM applications, CDR architectures, and protocols like PCIe, USB, and DP, while utilizing tools like Nanotime and Primetime for timing closure.

Skills

SerDes Analog Mixed-Signal Design CMOS FinFET SystemVerilog Matlab Python VerilogAMS PCIe USB MPHY CDR CTLE DFE LDO Primetime Nanotime Scripting Automation

What you'll do

Evaluate different circuit topologies for SerDes PHY requirements including Rx, CDR, Tx, and bias generators.
Execute transistor-level implementation and behavioral modeling for high-performance AMS circuits.
Drive mask design to implement the layout view of complex integrated circuits.
Create block-level specifications in coordination with architecture, SIPI, packaging, and board design teams.
Deliver IP views to SOC teams that meet strict quality, power, performance, and area standards.
Perform circuit modeling and performance evaluation using tools like SystemVerilog, Matlab, and Python.
Conduct lab testing, debugging, and data analysis for high-speed serial I/O.
Supervise layout, bench evaluation, and characterization from definition to high-volume production.

What we're looking for

Minimum requirement of a bachelor's degree.
Deep understanding of analog mixed-signal design with experience in high-speed serial links (preferred).
Experience designing analog mixed-signal circuit blocks such as Bandgap, LDOs, amplifiers, and ADCs (preferred).
Understanding of mismatch mitigation, linearity, stability, and low-power/low-noise techniques (preferred).
Experience with high-speed digital circuits and digitally assisted analog design concepts (preferred).
Knowledge of Tx/Rx equalization techniques, CDR architectures, and high-speed SerDes protocols (preferred).
Experience in AMS IC development from definition to production, including layout supervision and bench evaluation (preferred).
Experience with circuit modeling tools like SystemVerilog, Matlab, Python, or VerilogAMS (preferred).