Senior Emulation Engineer

Samsung Semiconductor

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
23 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $172k
$128k most similar roles pay here $228k

This role pays less than 65% of similar roles. Most pay $166,400–$216,250 — the shaded band above. At the midpoint, this role pays about $172k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Senior Emulation Engineer

The Senior Emulation Engineer joins the AGI Computing Lab to address complex system-level challenges posed by growing demands of future AI/ML workloads. You will build, bring up, and maintain large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs to enable pre-silicon validation. Key responsibilities include partitioning multi-million-gate designs, developing transactors and co-emulation environments, modeling memory subsystems, and running AI/ML workloads to validate performance. You will utilize tools such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce, alongside FPGA platforms like Synopsys HAPS or Cadence Protium. Required skills include proficiency in Verilog, SystemVerilog, and scripting languages like Tcl, Python, or Perl. The role focuses on solving hardware-software integration issues for high-performance computing while optimizing for capacity, run-time performance, and debug visibility across various standard interface protocols including PCIe, DDR/HBM, AXI/CHI, and Ethernet.

What you'll do

  • Build, bring up, and maintain large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs.
  • Partition and map multi-million-gate designs onto emulation systems and multi-FPGA prototypes to optimize performance and debug visibility.
  • Develop transactors, speed bridges, and co-emulation environments to connect designs to host software and physical interfaces.
  • Model memory subsystems, clock/reset schemes, and high-speed I/O interfaces for accurate pre-silicon emulation.
  • Enable early firmware, driver, and software bring-up by delivering stable targets with robust debug infrastructure.
  • Run AI/ML workloads and performance benchmarks pre-silicon to validate functionality and system-level performance.
  • Debug complex hardware and software issues using waveform capture and assertions to drive root-cause analysis.
  • Automate emulation and prototyping flows using scripting languages and agentic AI tools to improve turnaround time.

What we're looking for

  • Bachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years of experience.
  • Strong background in pre-silicon verification, validation, and SoC bring-up.
  • 5+ years of experience in FPGA prototyping and large-scale hardware emulation of complex ASIC/SoC designs.
  • Hands-on experience with platforms such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce.
  • Hands-on experience with FPGA platforms like Synopsys HAPS or Cadence Protium, including multi-FPGA partitioning and timing closure.
  • Experience with transactors, co-emulation (SCE-MI), speed bridges, and protocols such as PCIe, DDR/HBM, AXI/CHI, or Ethernet.
  • Proficiency in Verilog/SystemVerilog for design bring-up, clocking, reset, and memory modeling.
  • Proficiency in scripting (Tcl, Python, or Perl) for flow automation; familiarity with agentic AI tools is a plus.

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