Senior Post-Silicon PCIe Characterization Engineer

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Chandler, AZ
Salary
$161,500–$218,500 / yr
Posted
19 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $203k
This role $190k
$152k most similar roles pay here $253k

This role pays less than 54% of similar roles. Most pay $177,250–$229,612 — the shaded band above. At the midpoint, this role pays about $190k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

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At a glance

TL;DR · Senior Post-Silicon PCIe Characterization Engineer

As a Senior Post-Silicon PCIe Characterization Engineer on the Chandler Characterization team, you will validate and characterize next-generation Arm SoCs to help customers bring products to market. You will focus on characterizing silicon across process, voltage, temperature, and frequency conditions while collaborating with engineering teams to analyze results, debug issues, and improve performance. Your daily responsibilities include developing system-level stress workloads for Linux and Bare-Metal environments, creating test plans, and implementing tests to characterize silicon at the system level. You will utilize C/C++, Arm assembly, Python, and scripting languages while using protocol analyzers, scopes, and debuggers. The role requires expertise in PCIe architecture, including link initialization, training, equalization, and PHY operation. You will address technical challenges involving voltage and frequency margining, signal integrity, and high-speed interfaces like PCIe Gen4, Gen5, and Gen6.

What you'll do

  • Characterize next-generation Arm SoCs across process, voltage, temperature, and frequency conditions.
  • Develop and enable system-level stress workloads on Linux and Bare-Metal software environments.
  • Create test plans and implement tests to characterize silicon at the system level.
  • Debug and resolve complex system issues and hardware bugs.
  • Perform PCIe link initialization, training, equalization, and PHY operation characterization.
  • Conduct voltage and frequency margining to determine silicon operating limits.
  • Use protocol analyzers, scopes, and debuggers to troubleshoot PCIe and system issues.
  • Develop Python automation scripts for characterization and data analysis.

What we're looking for

  • Experience in pre- or post-silicon validation and characterization with an understanding of silicon power, performance, and PVT behavior.
  • Experience with PCIe architecture, including link initialization, training, equalization, and PHY operation.
  • Proficiency in C/C++, Arm assembly, Python, or other scripting languages.
  • Experience with voltage/frequency margining and identifying silicon operating limits.
  • Experience debugging PCIe, silicon, and system issues using protocol analyzers, scopes, debuggers, or similar tools.
  • Ability to analyze data, solve sophisticated problems, and communicate technical findings.
  • Experience with PCIe PHY characterization, signal integrity, and high-speed interfaces like Gen4, Gen5, or Gen6 (preferred).
  • Experience with PCIe performance, stability, protocol analysis, error handling, and Python automation for data analysis (preferred).

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