Senior Mixed Signal Design Engineer

Nvidia

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $216k

$135k $278k

below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $169,500–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1792 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1179 roles with salary data.

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At a glance

TL;DR · Senior Mixed Signal Design Engineer

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The Senior Mixed Signal Design Engineer joins a growing group responsible for handling challenging high-speed memory interface designs. In this role, you will perform mixed-signal and analog circuit builds for high-speed memory I/O interfaces, navigating the complexities of circuit development in deep submicron CMOS FinFET processes. You will lead designs through all stages of productization while collaborating with multi-functional teams to optimize performance. Key requirements include experience with LPDDR, DDR, GDDR, HBM, or SerDes designs, along with expertise in system-level timing budgets and device reliability. You will utilize Cadence custom design tools and simulators like Hspice, XA, FineSim, and Spectre. The work focuses on solving technical challenges in high-speed memory interfaces within deep submicron CMOS FinFET processes to ensure robust circuit implementation.

Skills

High Speed Memory SerDes CMOS FinFET LPDDR DDR GDDR HBM Cadence Hspice XA FineSim Spectre Verilog Nanotime Matlab ESD Latch-Up Power Delivery Board Design

What you'll do

Design mixed-signal and analog circuits for high-speed memory I/O interfaces.
Develop circuits using deep submicron CMOS FinFET processes.
Manage designs through all stages of the productization process.
Optimize designs in coordination with multi-functional teams.
Perform system-level timing budgets, specifications, and analysis.
Lead layout development while ensuring compliance with ESD, Latch-Up, and reliability rules.
Utilize Cadence custom design tools and various circuit simulators like Hspice and Spectre.

What we're looking for

BSEE, MSEE, or equivalent experience.
8+ years of high-speed memory (LPDDR, DDR, GDDR, HBM) or SerDes related design experience.
Experience with system-level timing budgets, specifications, and analysis.
In-depth understanding of deep submicron CMOS FinFET process and circuit design issues.
Familiarity with device reliability, ESD, and Latch-Up requirements.
Broad circuit design and implementation knowledge with significant depth.
Strong background in Cadence custom design tools and simulators like Hspice, XA, FineSim, and Spectre.
Working knowledge of package substrate, board design, and power delivery (preferred); Verilog, Nanotime, and Matlab (preferred).