Senior Mixed Signal Design Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$196,000–$310,500 / yr
Employment
Full-time
Posted
170 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k
This role $253k
$127k most similar roles pay here $330k

This role pays more than 90% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $253k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1150 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 912 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Mixed Signal Design Engineer

As a Senior Mixed Signal Design Engineer on the Mixed Signal team, you will lead the design and implementation of high-speed interface circuit projects, including high-frequency PLLs and transceivers. Your daily responsibilities involve designing, simulating, and verifying mixed-signal circuits while providing floorplan and layout guidelines to IC circuit and mask designers. You will manage designs through productization and collaborate with multi-functional teams to solve challenges in deep submicron CMOS processes. The role requires hands-on experience in silicon validation, debugging, characterization, and bring-up using lab instrumentation. Key technical requirements include proficiency in Cadence custom design tools, circuit simulators, timing analysis tools, Verilog, Matlab, Primetime, and Nanotime. You must possess deep expertise in Tx, Rx, CDR, and high-speed IO interfaces while addressing critical signal integrity and power integrity issues within the system level timing budget.

What you'll do

  • Lead the design and implementation of high-speed interface circuits including transceivers and PLLs.
  • Design, simulate, and verify mixed-signal circuits in deep submicron CMOS processes.
  • Supervise IC circuit and mask designers while providing floorplan and layout guidelines.
  • Perform silicon validation, debugging, characterization, and bring-up in a lab environment.
  • Manage the full lifecycle of designs from initial implementation through final productization.
  • Address complex challenges related to signal integrity and power integrity for high-speed IO.

What we're looking for

  • MS in Electrical Engineering or equivalent experience.
  • 4+ years of design experience in CMOS analog/mixed-signal circuit design.
  • Solid understanding of Cadence custom design tools, circuit simulators, and timing analysis tools.
  • Proven experience in crafting and mentoring designers.
  • Extensive experience in Tx, Rx, CDR, and PLL for high-speed IO interfaces.
  • In-depth understanding of deep submicron CMOS process and related circuit design issues.
  • Experience in silicon bring-up, debugging, and the use of lab instrumentation.
  • Knowledge in system level timing budget, signal integrity, and power integrity (preferred).

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