Senior Mixed Signal Design Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $196,000–$310,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $253k

$130k $330k

below market most similar roles pay here above market

This role pays more than 91% of similar roles. Most pay $169,500–$216,250 — the blue band above. At the midpoint, this role pays about $253k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1792 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1179 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Mixed Signal Design Engineer

Role Posting Log in to save

As a Senior Mixed Signal Design Engineer, you will join the Mixed Signal team to lead the design and implementation of high-speed interface circuits. Your daily responsibilities include designing, simulating, and verifying mixed-signal circuits, specifically high-speed transceivers and high-frequency PLLs. You will supervise IC circuit and mask designers, provide floorplan and layout guidelines, and support lab characterization of silicon. The role requires hands-on experience with silicon validation, debugging, and bring-up within deep submicron CMOS processes. You must possess expertise in Cadence custom design tools, circuit simulators, and timing analysis tools. Required technical skills include experience with Tx, Rx, CDR, and PLL for high-speed IO interfaces, along with knowledge of Verilog, Matlab, Primetime, and Nanotime to address signal integrity and power integrity challenges.

Skills

CMOS Mixed-Signal Circuit Design high speed transceivers PLL Cadence Verilog Matlab Primetime Nanotime Silicon Validation Timing Analysis Signal Integrity Power Integrity CDR Tx Rx Lab Instrumentation Floorplan Layout

What you'll do

Lead the design and implementation of high-speed interface circuits, including transceivers and high-frequency PLLs.
Perform design, simulation, and verification of mixed-signal circuits.
Supervise IC circuit and mask designers while providing floorplan and layout guidelines.
Conduct lab characterization of silicon and perform hardware debugging and bring-up.
Manage the full design lifecycle from initial implementation through final productization.
Address complex circuit design challenges specific to deep submicron CMOS processes.

What we're looking for

MS in Electrical Engineering or equivalent experience.
4+ years of design experience in CMOS analog / mixed-signal circuit design.
Extensive experience in Tx, Rx, CDR, and PLL for high-speed IO interfaces.
Proven experience in crafting and mentoring designers.
Experience in silicon bring-up, debugging, and use of lab instrumentation.
Solid understanding of Cadence custom design tools, circuit simulator, and timing analysis tools.
In-depth understanding of deep submicron CMOS process and related circuit design issues.
Knowledge in system level timing budget, signal integrity, and power integrity (preferred).