Senior Mixed Signal Design Engineer

Nvidia

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 117 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $216k

$136k $278k

below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $166,538–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Mixed Signal Design Engineer

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The Senior Mixed Signal Design Engineer joins the team to architect and implement high-speed Serdes reaching 80Gbps and beyond. This role involves full lifecycle ownership of transistor-level builds, including initial concept, schematic entry, layout, verification, and final silicon characterization. The engineer will optimize complex circuits for peak system performance by balancing noise, power, and loop stability in deep-submicron nodes. Key responsibilities include providing strategic floorplanning and high-speed routing mentorship while leading post-silicon bring-up and debugging. Candidates must demonstrate proficiency in Cadence Virtuoso and simulation tools like Spectre, HSpice, FineSim, or XA. Required expertise includes noise analysis, Monte Carlo simulations, and modeling for analog and digital circuits. The work focuses on high-speed data and clock path design using FinFET and deep-submicron CMOS processes.

Skills

SerDes FinFET CMOS Cadence Virtuoso Spectre HSpice FineSim XA Schematic Entry Layout Post-Silicon Bring-up Monte Carlo Simulation Noise Analysis Loop Stability High-Speed Routing Floorplanning

What you'll do

Architect high-speed Serdes architectures and transistor-level builds for data rates of 80Gbps and higher.
Drive the full silicon lifecycle from initial concept and schematic entry to layout and verification.
Optimize complex circuits for peak performance by balancing noise, power, and loop stability in deep-submicron nodes.
Provide strategic floorplanning and high-speed routing mentorship to layout engineers to ensure design integrity.
Lead post-silicon bring-up and debugging efforts to translate real-world data into build refinements.
Perform noise analysis, Monte Carlo simulations, and complex loop stability modeling.
Model the timing and functionality of both analog and digital circuits to streamline top-level verification.

What we're looking for

MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Minimum 5 plus years of professional Analog Build experience.
Deep portfolio in FinFET and deep-submicron CMOS processes.
Proficiency in the Cadence Virtuoso environment.
Mastery of simulation tools including Spectre, HSpice, FineSim, or XA.
Expertise in noise analysis, Monte Carlo simulations, and complex loop stability.
Rich experience in high-speed data and/or clock path design.
Proven ability in the modeling, timing, and functionality of both analog and digital circuits.

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