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Senior ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA +1 13 days ago $196,000–$310,500
Actively hiring Confirmed live today High trust Above market
Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development
10+ yrs exp
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Senior Staff Engineer, Physical Design (Floorplanning)

Samsung Electronics

Austin, TX 15 days ago $180,200–$270,400
Actively hiring Confirmed live today Trusted Above market
GPU Physical Design Place-and-Route Floorplanning Timing Closure STA Power-Grid Design DRC LVS FusionCompiler Innovus ICC2 PrimeTime Tempus StarRC RedHawk Python Tcl Shell Perl DTCO PPA Physical Verification Clock Tree Synthesis Synthesis
10+ yrs exp
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CPU Server Floorplan and Integration Engineer

Qualcomm

Santa Clara, CA 35 days ago $147,900–$221,900
Actively hiring Confirmed live today High trust Competitive pay
Physical Design Floorplanning Place and Route Static Timing Analysis (STA) Synthesis EMIR SoC) design RTL Design Power Grid Planning IP Integration Tapeout Flows Layout Design
2+ yrs exp
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ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA 57 days ago $116,000–$189,750
Actively hiring Confirmed live today High trust Below market
ASIC Floorplan Design VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design P&R Timing Closure Power/Clock Distribution Packaging
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Senior ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA +1 159 days ago $196,000–$310,500
Actively hiring Confirmed live today Trusted Above market
ASIC Floorplan Design VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design P&R Timing Closure Power/Clock Distribution Packaging
10+ yrs exp
Save