Senior Logic Design Engineer

Microsoft

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: —
Salary: $119,800–$234,700 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Closes: Apr 26, 2027

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k

This role $177k

$106k $248k

below market most similar roles pay here above market

This role pays less than 53% of similar roles. Most pay $171,000–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 692 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 649 roles with salary data.

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At a glance

TL;DR · Senior Logic Design Engineer

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The Senior Logic Design Engineer joins the Silicon Logic Design team within the Compute Silicon & Manufacturing Engineering organization to support the development of Azure Cobalt. In this role, you will design RTL for a high-performance PCIe Subsystem composed of multiple IPs, ensuring the subsystem meets specific SOC requirements. Daily responsibilities include refining implementations for area, power, and performance, performing design quality checks such as Synthesis, Lint, CDC, RDC, and Logic Equivalence, and driving solutions for timing critical paths. You will utilize tools and languages including Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, and Genus. The work involves managing dataflow and clocking requirements while utilizing UPF for low power intent and SDC commands for timing constraints.

Skills

RTL PCIe SoC Synthesis Lint CDC RDC Low Power Design Python Tcl Perl VCS VCLP Spyglass Questa Fusion Compiler Design Compiler Genus UPF SDC AXI APB ARM Fabric IPXACT Static Timing Analysis Computer Architecture

What you'll do

Build a PCIe subsystem composed of multiple IP blocks.
Collaborate with architecture and IP providers to ensure the subsystem meets SOC requirements.
Refine the implementation for area, power, and performance.
Perform design quality checks including Synthesis, Lint, CDC, RDC, and Logic Equivalence.
Drive solutions for timing critical paths based on dataflow and clocking requirements.
Automate engineering tasks using scripting for increased efficiency.

What we're looking for

Must have a Doctorate in a related field and 1+ years of technical engineering experience, or a Master's and 4+ years, or a Bachelor's and 5+ years.
Equivalent technical engineering experience to the degree requirements is accepted.
Must be able to pass the Microsoft Cloud Background Check.
Must provide proof of citizenship, US residency, or other protected status for export control eligibility.
Experience with high speed PCIe designs and protocols (preferred).
Experience with industry standard interface protocols such as AXI, APB, and ARM Fabric IPs (preferred).
Proficiency in EDA tools, scripting languages (Python, Tcl, Perl), and low power design principles (preferred).
Knowledge of Static Timing Analysis, clock crossing techniques, and SDC commands (preferred).

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