Senior DFT Engineer, Post Silicon

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 3 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $216k

$138k most similar roles pay here $278k

This role pays more than 73% of similar roles. Most pay $176,587–$219,150 — the shaded band above. At the midpoint, this role pays about $216k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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At a glance

TL;DR · Senior DFT Engineer, Post Silicon

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As a Senior DFT Engineer - Post-Silicon, you will drive the post-silicon enablement of DFT capabilities from initial silicon bring-up through production ramp and lifecycle support. You will develop data-driven approaches to analyze test results, quality indicators, yield behavior, and test efficiency while translating findings into technical recommendations. Your role involves influencing DFT architecture by communicating requirements early with clear metrics and what-if analysis. You will define methodologies for failure analysis, test-content validation, and production deployment while productizing new capabilities through scalable flows and debug procedures. The role requires expertise in scan, ATPG, and MBIST features alongside silicon characterization and manufacturing test. You must possess a deep understanding of semiconductor fundamentals, including device behavior and process variation, to solve complex problems related to test-time optimization, quality improvement, and yield learning for advanced chips.

Skills

DFT Scan ATPG MBIST Silicon Bring-up Failure Analysis test-content validation Yield Learning Manufacturing Test Production Test Dashboards

What you'll do

Drive post-silicon enablement of DFT capabilities from initial silicon bring-up through production ramp and lifecycle support.
Develop data-driven approaches to analyze test results, quality indicators, yield behavior, and test efficiency.
Influence DFT architecture by communicating post-silicon requirements early with clear metrics and what-if analysis.
Define and improve methodologies for silicon bring-up, failure analysis, test-content validation, and production deployment.
Productize new DFT capabilities by establishing scalable flows, validation criteria, debug procedures, and documentation.
Perform modeling and analysis to support test-time optimization, quality improvement, yield learning, and test power.
Align pre-silicon trade-offs with post-silicon execution by partnering across design, product development, and test teams.

What we're looking for

BSEE degree with 8+ years of experience in a related field.
MS degree with 6 years of experience in a related field.
Solid understanding of DFT concepts, silicon test, and the relationship between design implementation and post-silicon behavior.
Experience with silicon bring-up, debug, validation, production test, or engineering analysis of semiconductor devices.
Ability to analyze complex datasets using statistical or analytical approaches to identify trends and support decisions.
Familiarity with automated test environments and test-program flows.
Understanding of semiconductor fundamentals including device behavior, process variation, and operating conditions.
Strong written and oral communication skills for cross-functional collaboration.
Experience moving a silicon feature, test capability, or validation flow from development through production deployment (preferred).
Working knowledge of core DFT features like scan, ATPG, and MBIST with silicon characterization and manufacturing test (preferred).
Experience developing scalable engineering workflows, automation, dashboards, or analysis tools (preferred).

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