Senior DFT Silicon Validation Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
16 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $216k
$137k most similar roles pay here $278k

This role pays more than 77% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1047 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 833 roles with salary data.

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At a glance

TL;DR · Senior DFT Silicon Validation Engineer

As a Senior DFT - Silicon Validation Engineer on the Design-for-Test Engineering team, you will drive end-to-end DFT architecture and methodologies to accelerate post-silicon bring up and characterization for complex semiconductor chips. You will collaborate with multi-functional teams to define next-generation test strategies for ATE across the product roadmap while leading early silicon validation for SoCs. Your daily responsibilities include planning from architecture and development, performing chip validation on ATE, debugging test content, and analyzing silicon behavior under various operating conditions to identify failure root causes and ensure a strong production ramp. Required expertise includes silicon debug, bring-up, and productization of DFT features. You should possess skills in Perl, Python, or Tcl, along with knowledge of high-speed protocols, semiconductor process technology, and industry-standard DFT tools to solve challenges in advanced semiconductor technologies.

What you'll do

  • Implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
  • Develop and deploy DFT methodologies for next-generation products.
  • Define scan test plans, fault modeling, ATPG, and fault simulation.
  • Verify and validate test patterns and logic on complex, multi-million gate designs using vendor tools.
  • Perform silicon debug and bring-up on ATE with an understanding of pattern formats and failure processing.
  • Develop test programs and utilize scripting in Perl, Python, or Tcl for automation.
  • Mentor junior engineers on test designs and trade-offs regarding cost and quality.

What we're looking for

  • BSEE with experience, MSEE with , or PhD with in DFT or related domains.
  • Expertise in silicon debug and bring-up and productization of DFT features.
  • Demonstrated leadership in driving yield ramp and waste reduction for multiple products.
  • Hands-on experience in pre-silicon validation for various DFT features.
  • Outstanding written and oral communication skills.
  • Strong programming and scripting skills in Perl, Python, or Tcl (preferred).
  • Proven track record of implementing advanced DFT methodologies in groundbreaking semiconductor technologies (preferred).
  • Strong knowledge of high-speed protocols and semiconductor process technology (preferred).

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