This role pays less than
54%
of similar roles. Most pay
$168,500–$216,250
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$192k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
598 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 586 roles with salary data.
The Formal Design Verification Engineer joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization to support Microsoft’s cloud infrastructure. This role focuses on the verification of components used in Fabric Interconnect by developing formal-based verification environments, running simulations, and innovating methodologies to improve efficiency. The engineer will also integrate generative AI solutions into daily workflows while mentoring others. Key technical requirements include experience with pre-silicon subsystem or IP formal verification, specifically involving Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols. Candidates should be proficient in System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), and Python for post-processing. The work addresses critical hardware challenges including coherency, virtualization, security, interrupts, PCIe, CXL, and protocol bridges to ensure high-quality production of state-of-the-art computer chips like Azure Cobalt.
UVM
System Verilog
Python
C++
System C
SVA
Coverage Driven Verification
LLM
Prompt Engineering
RTL Simulation
4G/5G
3GPP
AXI
AHB
NoC
Bus Fabric
Perl
Automation
UVM
System Verilog
Python
C++
System C
SVA
coverage driven verification
Constraint Random Testing
LLM
Prompt Engineering
RTL Simulation
4G
5G
3GPP
AXI
AHB
NoC
Bus Fabric
Automation