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Firmware Development C C++ SoC Architecture Python SQL KQL RTOS PCIe Silicon Debug Bring-up Telemetry Crash Capture Memory Subsystems +9 more Show less

Embedded Firmware C C++ Python SQL KQL CI/CD JTAG GDB PCIe I2C SPI FPGA Silicon Bring-up root-cause analysis Telemetry Analysis Oscilloscope Logic Analyzer +13 more Show less

Verilog SystemVerilog Python TCL C FPGA Veloce Palladium JTAG ASIC Design Emulation Synthesis Place and Route Timing Closure SoC Architecture Kernel Debuggers Bus Protocols DDR NoC +14 more Show less

RTL JTAG Python C Assembly Perl Logic Analyzer Signal Generator ASIC Design SoC Architecture Pre-Si Post-Si Bring-up PVT Secure Boot +10 more Show less

RTL JTAG Python C Assembly Perl Logic Analyzer Signal Generator Pre-Si Post-Si SoC ASIC PVT Boot Configuration Secure Boot +10 more Show less

Verilog SystemVerilog Python TCL C FPGA Veloce Palladium JTAG ASIC Design SoC Architecture Timing Closure Synthesis Place and Route Kernel Debuggers Bus Protocols DDR NoC +13 more Show less

System Debug Root Cause Analysis Firmware BIOS UEFI BMC Signal Integrity Power Integrity Thermal Management Oscilloscopes Logic Analyzers System Architecture CPUs High-speed I/Os Power Delivery Automation +11 more Show less

C C++ Swift Operating Systems Embedded Systems GenAI System Architecture Silicon Bring-up Pre-silicon Simulation Failure Observability Crash Diagnostics +6 more Show less

GPU SoC Post-Silicon Debug System Validation Emulation Python C C++ Shell Scripting OpenGL OpenGL ES Vulkan Logic Analyzers Oscilloscopes Lauterbach Linux Android Verilog UVM AI/ML BIOS Firmware IPXACT +18 more Show less

ASIC Design RTL Pre-Si Post-Si JTAG Logic Analyzer Signal Generator Gen AI Silicon Validation SoC Debug +5 more Show less

Python C/C++ Linux Android Firmware Shell Scripting Verilog SoC GPU Post-Silicon Validation Logic Analyzer Lauterbach IPXACT Object Oriented Programming Power and Performance Analysis Design-for-Debug (DfD) +11 more Show less

RAS PCIe CXL Python C++ Perl Ruby JTAG SCAN Protocol Analyzers X86 micro architecture Post Silicon Validation MCA +8 more Show less

Python C++ Perl Ruby PCIe CXL DDR Memory RAS MCA MCE JTAG SCAN Protocol Analyzers Post Silicon Validation X86 micro architecture Debug Scripts SOC Micro-Controller +13 more Show less

C C++ Python Java Shell Scripting Windows Kernel ARM WinDbg JTAG QEMU UEFI ACPI BIOS Agile Scrum Multi-threading Performance Profiling +11 more Show less

Embedded Linux Yocto PetaLinux SystemVerilog Verilog VHDL Vivado Vitis Python C C++ Tcl Shell JTAG DDR5 LPDDR5 FPGA SoC Static Timing Analysis +14 more Show less

C C++ Python Linux Kernel RTOS GDB Trace32 JTAG Assembly Shell Perl ARM Cortex Hexagon DSP QNN Device Drivers Memory Management Automation Scripts +14 more Show less

Server Platform Debug SOC Debug Firmware Signal Integrity Power Sequencing Memory Training Triage Flows Boot Failures Instrumentation Electrical Engineering +5 more Show less

ASIC Design SoC Architecture RTL Design Verilog SystemVerilog FPGA Design Emulation Hardware Validation Hardware Debug C/C++ Python Tcl Perl Linux Embedded Linux CI/CD JTAG Git JIRA PCIe AXI Ethernet I2C Palladium Veloce MBIST ATPG +22 more Show less

SystemVerilog UVM SVA Python Perl C++ Assembly AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Power Management Clock Control RTL Simulation +12 more Show less

SystemVerilog UVM SVA Python C++ Assembly Perl AXI FPGA Emulation Formal Verification UPF Low Power Simulation Post-Silicon Debug +9 more Show less