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Active Keyword: Senior ASIC Design Verification Engineer Remove filter Clear all

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Senior ASIC Design Verification Engineer

Cisco

San Jose, CA 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP
7+ yrs exp
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Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA +5 35 days ago $168,000–$264,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS
8+ yrs exp Hybrid
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Senior Design Verification Engineer

Qualcomm

San Diego, CA 40 days ago $121,800–$182,600
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM Verilog VHDL Python C++ C Perl Formal Verification UPF AMBA AXI AHB APB ASIC Design RTL Object-oriented programming Automation
2+ yrs exp
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Senior ASIC Design Verification Infrastructure and Tools Engineer, GPU

Nvidia

Remote (Santa Clara, CA) +3 75 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis
5+ yrs exp Remote
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Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 92 days ago
Actively hiring Confirmed live today Trusted
System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification
5+ yrs exp Hybrid
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