Principal Physical Design Engineer

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
US
Salary
$142,800–$274,800 / yr
Posted
7 days ago
Freshness
Confirmed live today
Closes
Apr 25, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k
This role $209k
$127k $291k
below market most similar roles pay here above market

This role pays more than 57% of similar roles. Most pay $174,600–$229,468 — the blue band above. At the midpoint, this role pays about $209k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 636 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 591 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Principal Physical Design Engineer

JOB TITLE: Principal Physical Design Engineer The Principal Physical Design Engineer joins the Silicon Engineering team to work on Microsoft's Next-Gen AI SOC chip. This role involves delivering tool, flow, and methodology for physical design tasks at the block, sub-chip, and full-chip levels. Key responsibilities include leading Place and Route convergence, performing Static Timing Analysis, conducting Physical Verification, and managing Formal Equivalency Verification. The engineer will also design global clocking schemes, handle IR-Drop and EMIR analysis, and manage IP collaterals. Required skills include expertise in EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, and Cadence Innovus, alongside Siemens Calibre. Candidates must possess scripting skills in TCL and Python to optimize semiconductor design processes and deliver high-quality hardware products.

What does a Physical Design Engineer earn?

Median $183150 from 38 postings across 9 companies.

See salary data

What you'll do

  • Lead PnR convergence recipe development for designs at block, subsystem, and sub-chip levels.
  • Develop and implement methodologies to improve physical design efficiency, performance, and sign-off.
  • Execute static timing analysis, physical verification, functional logic equivalence, and low power verification.
  • Implement functional and timing ECOs with minimal physical design impact.
  • Design and implement global clocking schemes at the SOC and sub-chip levels.
  • Install and perform quality checks on internal and external IP collaterals.
  • Conduct physical design reviews to identify and resolve design issues for the engineering team.

What we're looking for

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
  • Must provide proof of citizenship, US residency, or other protected status for export control access.
  • Experience in tapeouts of complex ASICs in leading edge technology (preferred).
  • 10+ years of experience in blocks level place and route (preferred).
  • Expertise in physical design EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, and Cadence Innovus; Siemens Calibre (preferred).

More like this

Similar roles

Principal Physical Design Engineer

Microsoft

14 days ago $165,600–$296,400
Physical Design Silicon Design Synthesis Place and Route Clock Construction CTS Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification RTL to GDS PPA Floorplanning Extraction Tape-out
10+ yrs exp Hybrid

Lead Physical Design Engineer

Amd

Santa Clara, CA 43 days ago $210,400–$315,600
ASIC Physical Design Static Timing Analysis clock-tree synthesis ECO PPA Optimization Synopsys ICC2 Fusion Compiler Cadence Innovus PrimeTime RedHawk Formality Conformal TCL Python Perl Pandas Machine Learning Formal Verification Physical Verification

Physical Design Engineer

Qualcomm

San Diego, CA +2 48 days ago $123,100–$250,000
ASIC Design Physical Design Place and Route Static Timing Analysis Clock Tree Synthesis Floorplanning Power Planning Signal Integrity Analysis Physical Verification DFT Low Power Design UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime RC Extraction ECO Implementation
4+ yrs exp

Physical Design Engineer

Qualcomm

San Diego, CA 16 days ago $174,400–$261,600
ASIC SoC Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python Perl TCL C/C++ Shell Scripting Linux Unix Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis
10+ yrs exp

Physical Design Engineer

Broadcom

San Jose, CA 5 days ago $82,500–$132,000
ASIC Physical Design Floorplanning Place and Route Clock Tree Synthesis Static Timing Analysis Physical Verification DRC LVS ERC IR Drop Electromigration TCL Python Ruby Bash Cadence Innovus Synopsys IC Compiler II DFT UPF CPF FinFET 2.5D/3D Integration CoWoS HBM3/4
2+ yrs exp

Principal Physical Design Engineer

Broadcom

San Jose, CA 5 days ago $143,800–$230,000
Cadence Innovus Synopsys PrimeTime Cadence Tempus Siemens Calibre RedHawk StarRC QRC Python TCL Unix Shell Scripting STA IR-drop EM UPF CPF GDSII Place and Route CTS Floorplanning Multi-patterning 2.5D/3D Integration HBM3/4 CoWoS
10+ yrs exp