Principal Physical Design Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $143,800–$230,000 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Closes: Apr 28, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k

This role $187k

$131k $262k

below market most similar roles pay here above market

This role pays less than 60% of similar roles. Most pay $174,600–$229,468 — the blue band above. At the midpoint, this role pays about $187k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Principal Physical Design Engineer

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The Principal Physical Design Engineer joins the Physical Design team within the ASIC Products Division to lead implementation for next-generation AI/ML accelerators, high-performance networking, and custom cloud ASICs. This role involves driving full-flow implementation from floorplanning to GDSII stream-out, including synthesis, Place and Route, clock tree synthesis, and timing closure. The engineer will perform multi-corner multi-mode static timing analysis, signal integrity optimization, and power grid optimization for signoff. Key technical requirements include proficiency with Cadence Innovus, Synopsys PrimeTime, Cadence Tempus, StarRC, QRC, RedHawk, and Siemens Calibre. Candidates must possess expertise in advanced technology nodes like N5, N3, and N2, utilizing TCL, Python, and Unix shell scripting. The work addresses complex compute and bandwidth challenges using 2.5D/3D chiplet integration and multi-patterning.

What does a Physical Design Engineer earn?

Median $183150 from 38 postings across 9 companies.

See salary data

Skills

Cadence Innovus Synopsys PrimeTime Cadence Tempus Siemens Calibre RedHawk StarRC QRC Python TCL Unix Shell Scripting STA IR-drop EM UPF CPF GDSII Place and Route CTS Floorplanning Multi-patterning 2.5D/3D Integration HBM3/4 CoWoS

What you'll do

Lead block-level and top-level physical implementation from floorplanning to GDSII stream-out.
Drive floorplanning, placement, CTS, routing, and timing/power optimization on 5nm, 3nm, and 2nm nodes.
Perform multi-corner multi-mode (MCMM) static timing analysis (STA) and signal integrity optimization.
Execute power grid optimization for static and dynamic IR-drop and EM using PrimeTime, Voltus, or RedHawk.
Manage complex multi-patterning and metal stack requirements for advanced technology nodes.
Develop and maintain in-house automation and methodology flows using TCL, Python, and Unix shell scripting.
Implement high-speed clock networks including H-tree, mesh, and low-power CTS.
Execute power-aware implementation flows for multi-voltage domains and clock/power gating.

What we're looking for

B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
12+ years of hands-on physical design experience taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
High proficiency in Cadence Innovus for P&R, Synopsys PrimeTime or Cadence Tempus for STA, and RedHawk for IR/EM.
Proficiency in StarRC / QRC for extraction and Siemens Calibre for DRC/LVS.
Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS) (preferred).
Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating) (preferred).

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