Principal DFT Engineer

SpaceX

Confirmed live yesterday Low trust

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Work type
On-site
Location
Austin, TX
Posted
43 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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TL;DR · Principal DFT Engineer

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The Principal DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role involves leading the implementation and optimization of DFT architectures, including scan insertion, compression logic, and memory BIST using Siemens Tessent tools. The engineer will own ATPG tools and methodologies to generate patterns for stuck-at, transition, and path delay fault models while providing post-silicon testing support. Key responsibilities include evaluating design readiness through RTL and physical design DRC tools, integrating DFT fabrics into subsystems, and running gate level simulations. Candidates should possess expertise in Verilog, SystemVerilog, and programming languages like Perl, Python, Tcl, or C+. The role addresses the technical challenge of ensuring reliable connectivity via high-speed, low-power silicon components designed for complex orbital and terrestrial environments.

Skills

DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog Python Perl Tcl RTL UPF Gate Level Simulation SDF Formal Verification ATE

What you'll do

  • Lead implementation and optimization of DFT architectures including scan insertion, compression, and BIST using Siemens Tessent tools.
  • Own ATPG tools and methodologies to generate patterns for stuck-at, transition, and path delay fault models.
  • Evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within various subsystems.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Develop test scripts and automate processes using programming languages like Perl, Python, Tcl, or C++.
  • Provide post-silicon testing and validation support to ensure chip reliability.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience working with ASICs.
  • 10+ years of experience in scan insertion and DFT setup, integration, and validation.
  • Experience leading SOC DFT execution from concept through tapeout and product deployment.
  • Proficiency in RTL to understand, trace, and debug connectivity issues as they pertain to DFT.
  • Ability to solve complex problems including clock domain crossings and power optimization.
  • Experience with UPF, formal verification, and DRC rule checking.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.

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