Principal DFT Engineer

SpaceX

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Work type
On-site
Location
Austin, TXIrvine, CAPalo Alto, CA
Posted
89 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Principal DFT Engineer

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The Principal DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on maximizing the performance of the Starlink network by enabling reliable connectivity in previously inaccessible locations. The engineer will lead the implementation and optimization of DFT architectures, including scan insertion, memory BIST, and logic BIST. Key responsibilities involve owning ATPG tools and methodologies for stuck-at, transition, and path delay fault models, while providing post-silicon testing support. The position requires proficiency with Siemens Tessent tools, Verilog, SystemVerilog, and programming languages like Perl, Python, Tcl, or C++. Candidates must manage design readiness through RTL and physical design DRC tools, handle clock domain crossings, and utilize UPF for power optimization.

Skills

DFT ASIC Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST RTL Verilog SystemVerilog Python Perl Tcl UPF Formal Verification DRC ATE SDF Gate Level Simulation

What you'll do

  • Lead implementation and optimization of DFT architectures including scan insertion, compression, and BIST.
  • Own ATPG tools and methodologies to generate patterns for stuck-at, transition, and path delay fault models.
  • Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
  • Integrate and verify DFT fabrics and IP within subsystems.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Develop test scripts and automate processes using Perl, Python, Tcl, or C++.
  • Provide post-silicon testing and validation support.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience working with ASICs.
  • 10+ years of experience in scan insertion and DFT setup, integration, and validation.
  • Leadership experience driving SOC DFT execution from concept through tapeout and product deployment (preferred).
  • RTL experience to understand, trace, and debug RTL connectivity issues as they pertain to DFT (preferred).
  • Ability to solve complex problems including clock domain crossings and power optimization (preferred).
  • Experience with UPF, formal verification, and DRC rule checking (preferred).
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for required Department of State authorizations.

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