Principal DFT Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CAAustin, TXIrvine, CA
Salary
$220,000–$355,000 / yr
Posted
89 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k
This role $288k
$143k $378k
below market most similar roles pay here above market

This role pays more than 95% of similar roles. Most pay $177,300–$243,500 — the blue band above. At the midpoint, this role pays about $288k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Principal DFT Engineer

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The Principal DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on maximizing the utility of the Starlink network by expanding performance and connectivity capabilities. Key responsibilities include leading the implementation and optimization of DFT architectures, including scan insertion, compression, memory BIST, and logic BIST. The engineer will own ATPG tools and methodologies for generating patterns for stuck-at, transition, and path delay fault models while providing post-silicon testing support. Required technical skills include experience with Siemens Tessent tools, RTL, Verilog, SystemVerilog, and programming languages like Perl, Python, Tcl, or C++. The role involves solving complex problems regarding clock domain crossings, power optimization, and UPF while ensuring design readiness through Scan Design Rule Check tools.

Skills

DFT ASIC Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST Python Perl Tcl Verilog SystemVerilog RTL UPF Formal Verification DRC ATE SDF Gate Level Simulation

What you'll do

  • Lead implementation and optimization of DFT architectures including scan insertion, compression, and BIST.
  • Own ATPG tools and methodologies to generate patterns for stuck-at, transition, and path delay fault models.
  • Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
  • Integrate and verify DFT fabrics and IP within subsystems.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Develop test scripts and automate processes using Perl, Python, Tcl, or C++.
  • Provide post-silicon testing and validation support.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience working with ASICs.
  • 10+ years of experience in scan insertion and DFT setup, integration, and validation.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Leadership experience driving SOC DFT execution from concept through tapeout and product deployment (preferred).
  • RTL experience to understand, trace, and debug RTL connectivity issues as they pertain to DFT (preferred).
  • Experience with UPF, formal verification, and DRC rule checking (preferred).

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