Principal DFT Engineer

SpaceX

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$220,000–$355,000 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $288k
$140k most similar roles pay here $378k

This role pays more than 95% of similar roles. Most pay $176,687–$228,375 — the shaded band above. At the midpoint, this role pays about $288k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Principal DFT Engineer

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The Principal DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on implementing and optimizing DFT architectures, including scan insertion, compression logic, memory BIST, and logic BIST using Siemens Tessent tools. The engineer will own ATPG tools and methodologies to generate patterns for stuck-at, transition, and path delay fault models while providing post-silicon testing support. Key responsibilities include evaluating design readiness via RTL and physical design DRC tools, integrating DFT fabrics into subsystems, and running gate level simulations. Candidates should possess expertise in Verilog, SystemVerilog, and programming languages like Perl, Python, Tcl, or C++. The role addresses the technical challenge of ensuring reliable connectivity through advanced silicon processes for high-speed, low-power consumption hardware within a global satellite network.

Skills

DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE

What you'll do

  • Lead implementation and optimization of DFT architectures including scan insertion, compression logic, and memory BIST.
  • Manage ATPG tools and methodologies to generate patterns for stuck-at, transition, and path delay fault models.
  • Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
  • Integrate and verify DFT fabrics and IP within various subsystems.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Develop test scripts and automate processes using Perl, Python, Tcl, or C++.
  • Provide post-silicon testing and validation support for advanced ASICs.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience working with ASICs.
  • 10+ years of experience in scan insertion and DFT setup, integration, and validation.
  • Experience leading SoC DFT execution from concept through tapeout and product deployment.
  • Proficiency in RTL to understand and debug connectivity issues as they pertain to DFT.
  • Ability to solve complex problems including clock domain crossings and power optimization.
  • Experience with UPF, formal verification, and DRC rule checking.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.

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