Design Verification Engineer

What you'll do

• Verify the functionality and performance of premier System-on-Chip (SoC) designs and subsystems.
• Review design and architecture specifications to ensure high quality and performance goals are met.
• Develop comprehensive test plans, coverage plans, and next-generation verification methodologies.
• Build and maintain complex testbenches for various IP blocks like Neural Engines or memory controllers.
• Drive test cases by analyzing use cases and corner conditions with design and software teams.
• Implement constrained random verification processes and functional coverage using SystemVerilog and UVM.
• Utilize Python, Perl, or other scripting languages to automate and streamline the verification process.

What we're looking for

• Bachelor of Science degree and at least 3 years of relevant industry experience.
• Skilled in digital verification including constrained random, functional coverage, code coverage, and assertion methodology (preferred).
• Knowledge of SystemVerilog, digital simulation, and debug (preferred).
• Knowledge of computer architecture and digital design fundamentals (preferred).
• Software programming skills with knowledge of data structures and algorithms (preferred).
• Experience with Python, Perl, or similar scripting languages (preferred).
• Knowledge of verification methodologies like UVM (preferred).
• Experience with C/C++ and assembly is a plus (preferred).