This role pays more than
61%
of similar roles. Most pay
$177,737–$231,000
— the shaded band above.
At the midpoint, this role pays about
$209k
versus about
$204k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
668 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 647 roles with salary data.
Principal Design Engineer - IP Office
The Principal Design Engineer - IP Office joins the Artificial Intelligence System on Chip (AISoC) Silicon team to drive the development of AI components. This role focuses on best-in-class IP selection, quality assurance, and seamless integration into SoCs. The engineer is responsible for identifying high-value IPs in areas such as PLL, DTS, Droop-Detector, HBM4, 224G Ethernet, and GPIOs while architecting robust processes for release, update, and pre/post silicon validation. They will collaborate with architecture, physical design, and design for test teams to optimize trade-offs regarding signal and power integrity. The role requires expertise in deep sub-micron technologies, front-end and back-end integration flows, and proficiency in scripting languages like Python or Perl. This position addresses the technical challenge of integrating complex components into high-performance AI accelerator systems.
Identify and select best-in-class IPs for components like PLL, DTS, HBM4, and high-speed Ethernet.
Architect robust processes for IP release, updates, quality assurance, and pre/post-silicon validation.
Track IP releases and updates to ensure seamless integration into the SoC design.
Review IP integrations, signal/power integrity, and package designs with internal teams and external vendors.
Ensure high-quality incoming IPs by collaborating closely with logic and physical design teams.
Interface with architecture, physical design, and DFT teams to optimize technical trade-offs.
Provide technical leadership through mentorship and cross-functional teamwork.
What we're looking for
A Doctorate and 3+ years of experience, a Master's and 6+ years of experience, or a Bachelor's and 8+ years of experience in a related field.
Ability to pass the Microsoft Cloud Background Check every two years.
Must provide proof of citizenship, residency, or other protected status to access export-controlled information.
10+ years of experience in interaction with major IP suppliers, selection, QA, and integration for CPU, GPU, or AI accelerator SoCs (preferred).
6+ years of design experience in SRAM, high-speed serial/parallel IOs, or sub-system and SoC integration (preferred).
5+ years of experience as a leader of IP office functions for major CPU, GPU, or AI SoCs (preferred).
Established reputation with suppliers of 112G/224G Ethernet, PCIe 5/6, and HBM3/4 (preferred).
Proficiency in scripting languages like Python or Perl; knowledge of front-end and back-end IP integration flows; and strong communication skills (preferred).
Electro-mechanical Systems
Digital Electronics
Power Electronics
PCB Layout
Altium
Microcontrollers
DSPs
FPGAs
Ethernet
SPI
I2C
UART
CAN
RS-485
USB
SolidWorks
FEA
EMC Testing
Design for Manufacturability