Principal IC Design Engineer

Broadcom

Quick summary

Work type
On-site
Location
Broomfield, CO · Mendota Heights-Northland
Salary
$127,100–$203,400 / yr
Posted
15 days ago
Closes
Oct 21, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $165k
$116k most similar roles pay here $232k

This role pays less than 72% of similar roles. Most pay $165,000–$216,250 — the shaded band above. At the midpoint, this role pays about $165k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Principal IC Design Engineer

Broadcom’s ASIC Product Division seeks a senior SOC engineer to join its high-performance team, responsible for designing and integrating IP on cutting-edge SOCs. This role involves defining SOC architecture, conducting detailed design analysis with advanced tools, leading simulation and verification efforts, collaborating with internal and external teams, optimizing area and performance through layout engineering consultation, setting DRAM system timing budgets, and generating comprehensive documentation for IP releases. Ideal candidates possess extensive experience in high-performance DRAM interface design, SOC architecture, and HDL languages like Verilog, VHDL, and SystemVerilog. They should also have a strong grasp of physical implementation, timing closure, signal integrity, and cloud-based collaboration tools, along with the ability to make data-driven decisions and excel in cross-functional teams.

What you'll do

  • Define the overall SOC architecture for high-performance SOCs.
  • Lead detailed design analysis using advanced tools to ensure quality.
  • Support simulation, synthesis, formal verification, and validation processes.
  • Optimize area and performance by consulting with layout engineers.
  • Align DRAM system timing budget goals with product requirements.
  • Generate comprehensive collateral including design specifications for IP release.

What we're looking for

  • Strong understanding and experience with high performance DRAM interface design.
  • Experience with SOC architecture and memory interface integration.
  • Expertise in HDL languages (Verilog, VHDL, SystemVerilog).
  • Excellent communication and cross-functional collaboration skills.
  • Ability to analyze complex trade-offs and make data-driven decisions.
  • Strong understanding of physical implementation and timing closure.

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