Principal IC Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Broomfield, COMendota Heights, MN
Salary
$129,400–$207,000 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Closes
Oct 21, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k
This role $168k
$114k most similar roles pay here $274k

This role pays less than 81% of similar roles. Most pay $177,037–$231,725 — the shaded band above. At the midpoint, this role pays about $168k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Principal IC Design Engineer

Role Posting Log in to save

As a Principal IC Design Engineer within the ASIC Product Division, you will join the SOC team to design and integrate IP onto high volume and high performance SOCs. You will participate in defining overall SOC architecture, lead extended teams through simulation, synthesis, formal verification, constraint definition, and validation, and collaborate with internal and external teams for customer success. Your daily work involves refining solutions with layout engineers to optimize area and performance while defining DRAM system timing budget goals. You must possess expertise in Verilog, VHDL, and SystemVerilog, alongside a strong understanding of physical implementation, timing closure with process variation, and signal integrity impacts. This role focuses on the technical challenge of integrating memory interfaces into complex SOC architectures for advanced semiconductor products using leading edge tools and cloud based documentation systems.

Skills

Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL

What you'll do

  • Participate in defining the overall SOC architecture.
  • Perform detailed design analysis using leading-edge tools to ensure quality.
  • Lead an extended team to support simulation, synthesis, formal verification, and validation.
  • Consult with layout engineers to optimize area and performance for refined solutions.
  • Define DRAM system timing budget goals aligned with product requirements.
  • Generate technical collateral and documentation to support IP releases.

What we're looking for

  • Must have legal authorization to work in the US.
  • Bachelor's degree in Engineering (EE, CE, or CS preferred) and 12+ years of related experience.
  • Master's degree in Engineering and 10+ years of related experience.
  • Strong understanding and experience with high performance DRAM interface design.
  • Experience with SOC architecture and memory interface integration.
  • Demonstrated expertise in HDL languages including Verilog, VHDL, and SystemVerilog.
  • Strong understanding of physical implementation, timing closure, and signal integrity.
  • Excellent communication skills and ability to perform cross-functional collaboration.

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