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Physical Design Timing Engineer (STA)

Broadcom

San Jose, CA 15 days ago $141,300–$226,000
Actively hiring Verified listing Competitive pay
Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools
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CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 99 days ago $198,700–$298,100
Actively hiring Above market
TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction
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