Careers

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CA
Posted
5 days ago
Closes
Nov 28, 2026

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Similar $191k
$143k most similar roles pay here $234k

This listing doesn't post a salary. Most similar roles pay $165,150–$216,262.

Based on 240 similar postings.

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About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 270 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 196 roles with salary data.

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At a glance

TL;DR · Careers

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As a CPU Physical Design Timing Engineer at Qualcomm Technologies, Inc., you will join the NUVIA team to define and develop timing closure for Oryon CPU cores, collaborating closely with microarchitecture and RTL design teams to ensure aggressive power, area, and performance goals are met. Your daily tasks include setting up STA constraints, conducting timing analysis across various PVT conditions using tools like PT/Tempus, and optimizing flows through scripting within STA/PD tools. You will also work on automating methodologies and collaborating with Qualcomm’s central timing technology team to drive CPU implementation projects forward. This role requires expertise in STA basics, AOCV/POCV concepts, CTS, and managing timing constraints, along with hands-on experience using Prime-time, Tempus, ICC2, Innovus, and scripting languages like TCL, Perl, and Python.

Skills

TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS TCL scripting Perl scripting Python scripting ASIC back-end design flows Cross-talk noise Signal Integrity Layout Parasitic Extraction Feed through handling

What you'll do

  • Define and develop timing constraints for Oryon CPU Cores.
  • Conduct timing analysis and validation across various PVT conditions using PT/Tempus.
  • Optimize STA flow and correlate Spice to STA results.
  • Debug root causes of timing miscorrelation at different design levels.
  • Evaluate and implement multiple timing methodologies on diverse technology nodes.
  • Develop automation scripts within STA/PD tools for methodology advancement.

What we're looking for

  • Extensive experience in STA timing analysis and managing timing constraints.
  • Proficiency in Prime-time and Tempus tools for STA flow optimization.
  • Hands-on expertise in driving timing convergence at chip-level and hard-macro level.
  • Strong scripting skills with TCL, Perl, and Python for automation.
  • In-depth knowledge of ASIC back-end design flows and methods (ICC2, Innovus).
  • Experience in cross-talk noise, signal integrity, and layout parasitic extraction.

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