Physical Design Sign-off Engineer

What you'll do

• Develop full-stack web applications to power the Signoff infrastructure across all SOC design groups.
• Build and enhance Signoff dashboards, CAD flow metrics collection, and data visualization tools.
• Develop backend services and APIs using Python and JavaScript/TypeScript.
• Create interactive frontend dashboards for design and CAD teams.
• Manage and query enterprise-scale design data using SQL databases.
• Integrate RAG capabilities and AI-powered features into the Signoff platform.
• Provide technical support for Signoff infrastructure to improve internal processes.

What we're looking for

• BS in Computer Science or related field with 10+ years of relevant industry experience.
• Proficiency in programming using Python, Perl, or Tcl.
• Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.
• Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon.
• Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction.
• Understanding of PPA tradeoffs and experience defining implementation recipes to improve power, performance, and area.
• Background in Chip Design, Chip Verification, or CAD (preferred).
• Experience with LLM integration, RAG pipelines, vector databases, containers, Kubernetes, or monitoring tools (preferred).