Physical Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $174,149–$194,700 / yr
Posted: 1 day ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $184k

$137k most similar roles pay here $274k

This role pays less than 61% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $184k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer, you will collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. You will be responsible for the hands-on physical implementation and timing closure of core platforms and SoCs, moving from net list to GDS2 implementation while meeting specific schedule goals. Your daily work involves performing timing, physical, and electrical verification, as well as generating and implementing ECOs to rectify noise, EM, IR, and timing violations. You will optimize PnR partitions for Power, Performance, and Area while streamlining signoff criteria and developing auto ECO scripts. To succeed, you must utilize tools like ICC, ICC2, or Innovus; Synopsys PrimeTime; and Voltus or Redhawk. Proficiency in TCL, Perl, Python, and Unix scripting is required to improve execution efficiency and manage data.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

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Skills

PnR ICC2 Innovus PrimeTime TCL Python Perl Unix EMIR Voltus Redhawk Calibre floor planning Timing Closure Scripting

What you'll do

Drive physical design aspects of partition architecture early in the design cycle.
Execute full netlist to GDS2 implementation while meeting schedule and design goals.
Perform timing, physical, and electrical verification to achieve signoff closure for partitions.
Generate and implement ECOs to rectify timing, noise, and EM/IR violations.
Optimize PnR partitions to achieve the best Power, Performance, and Area (PPA).
Develop and enhance auto ECO generation scripts using TCL, Perl, or Python.
Resolve design and flow issues related to physical design and execution.
Analyze results from EMIR and Physical verification tools to address violations.

What we're looking for

Master's degree or foreign equivalent in Electrical and Computer Engineering, or a related field.
Experience using PNR tools like ICC, ICC2, or Innovus for floor planning, placement, clock optimization, routing, timing, and power optimization.
Experience using Synopsys PrimeTime for timing analysis and timing ECO generation for SoC partitions.
Proficiency in TCL, Perl, Python, and Unix scripting to summarize data and implement custom scripts.
Understanding of physical design construction and analysis flow to execute and signoff on SoCs.
Understanding of transistors and digital circuits to make trade-offs during implementation and closure.
Ability to interpret results from EMIR analysis tools like Voltus or Redhawk to address violations.
Ability to use Physical verification tools like Calibre to identify and fix violations.