Physical Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $101,400–$152,200 / yr
Posted: 4 days ago
Freshness: Confirmed live today
Closes: May 1, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $127k

$86k $245k

below market most similar roles pay here above market

This role pays less than 92% of similar roles. Most pay $162,000–$223,000 — the blue band above. At the midpoint, this role pays about $127k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$218,400 across 551 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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JOB TITLE: Physical Design Engineer The Physical Design Engineer joins the ASICS Engineering group to support the SoC and ASIC Design organization. This role involves executing the full physical design flow from synthesized netlist to tape-out for high-performance computing, AI, mobile, and automotive semiconductor technologies. Key responsibilities include floorplanning, partitioning, power planning, IR-drop analysis, placement, clock tree synthesis, routing, and timing optimization across Multi-Mode Multi-Corner scenarios. The engineer must resolve timing violations, signal integrity issues, and crosstalk effects while performing RC extraction and physical verification. Required skills include experience with Cadence Innovus, Synopsys Fusion Compiler, and Synopsys PrimeTime SI. Candidates should possess proficiency in Python, Perl, TCL, Shell scripting, and C/C++ within Linux/Unix environments to develop automation tools and implement low-power design methodologies for advanced process technologies.

What does a Physical Design Engineer earn in California?

Median $177300 from 31 postings across 8 companies.

See salary data

Skills

ASIC Design Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Static Timing Analysis Clock Tree Synthesis Floorplanning Place and Route RC Extraction Physical Verification Formal Verification Python Perl TCL Shell Scripting C/C++ Linux Unix IR-drop Analysis Signal Integrity

What you'll do

Execute all stages of the physical design flow from synthesized netlist to tape-out.
Perform floorplanning, partitioning, power planning, and IR-drop analysis for complex ASICs and SoCs.
Execute placement, clock tree synthesis, routing, and timing optimization across MMMC scenarios.
Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
Perform RC extraction, physical verification, and formal verification activities.
Implement engineering change orders and support design convergence through sign-off.
Develop automation and productivity tools using scripting languages and software development techniques.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
2-10+ years of industry experience or relevant academic/project experience in Physical Design.
Experience in ASIC/SoC Physical Design implementation (preferred).
Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler (preferred).
Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI (preferred).
Experience with physical verification, design sign-off, and formal verification methodologies (preferred).
Experience with low-power design, clock tree synthesis, and signal integrity analysis (preferred).
Proficiency in Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments (preferred).

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