Senior Staff HW SOC/ASIC Physical Design Engineer

Qualcomm

Confirmed live 3 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
8 days ago
Freshness
Confirmed live 3 days ago
Closes
Apr 24, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $152k
$109k $243k
below market most similar roles pay here above market

This role pays less than 87% of similar roles. Most pay $165,675–$216,250 — the blue band above. At the midpoint, this role pays about $152k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 594 open roles on FindRole.

Listed pay typically runs $147,900–$219,400 across 568 roles with salary data.

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At a glance

TL;DR · Senior Staff HW SOC/ASIC Physical Design Engineer

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The HW SOC/ASIC Physical Design Engineer, Senior/Staff joins the ASICS Engineering team to execute the RTL-to-GDSII flow for complex designs. This role involves architecting and implementing robust, power-efficient clock distribution networks while driving timing closure across multiple corners and modes. Key responsibilities include floorplanning, placement, clock tree synthesis, and routing using industry-standard tools like Innovus and ICC2. The engineer will perform static timing analysis with PrimeTime and Tempus, conduct physical verification using Calibre and Pegasus, and develop automation scripts in TCL, Python, and Perl. The position requires expertise in FinFET technologies at 7nm, 5nm, and 3nm nodes. The work focuses on optimizing power, performance, and area while ensuring compliance with foundry design rule manuals for successful tapeout.

Skills

ASIC Design RTL-to-GDSII Floorplanning Clock Tree Synthesis Place-n-Route Static Timing Analysis DRC LVS TCL Python Perl Innovus ICC2 PrimeTime Calibre Pegasus ICV UPF CPF SDC FinFET EM/IR Analysis Virtuoso Formal Equivalence

What you'll do

  • Execute floorplanning, placement, clock tree synthesis, and routing using industry-standard EDA tools.
  • Drive timing closure across multiple corners and modes using static timing analysis tools.
  • Perform full-chip and block-level physical verification including DRC, LVS, ERC, and antenna checks.
  • Develop and maintain automation scripts in TCL, Python, or Perl for verification and reporting flows.
  • Implement low-power architectures by developing power intent files and integrating power-aware features.
  • Debug and resolve physical verification violations, timing risks, and power domain issues.
  • Perform GDS-to-GDS comparisons to validate ECO changes and ensure tapeout readiness.

What we're looking for

  • Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
  • Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC experience, OR Master's with 1+ year, OR a PhD.
  • 3+ years of experience in physical design with a focus on clock tree design and implementation.
  • Proficiency with EDA tools for CTS, STA, and physical verification such as ICC2, Innovus, and PrimeTime.
  • Solid scripting skills in TCL, Python, and Perl for flow automation and data analysis.
  • Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.
  • Familiarity with low-power design techniques, including clock gating and multi-voltage domains.
  • Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies (preferred).

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