Physical Design Engineer II (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $155,000–$185,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $174k

This role $170k

$131k most similar roles pay here $222k

This role pays less than 53% of similar roles. Most pay $144,500–$202,850 — the shaded band above. At the midpoint, this role pays about $170k versus about $174k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer II (Silicon Engineering)

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As a Physical Design Engineer II in the Silicon Engineering team, you will work on advanced RTL2GDSII physical design and flow development, collaborating closely with other engineers to ensure high-quality chip designs. Your day-to-day responsibilities include leveraging industry-standard EDA tools for layout synthesis, placement, routing, and verification while adhering to CMOS digital design principles. You must possess a deep understanding of standard cell libraries and their functionality, along with knowledge of DFT/Scan/LBIST techniques and their impact on physical design flows. This role requires proficiency in scripting languages such as Perl or Python for automation tasks and familiarity with UNIX/Linux environments. The position is part of a fast-paced semiconductor company tackling complex challenges at the cutting edge of technology.

Skills

EDA tools CMOS digital design principles standard cells DFT Scan MBIST LBIST RTL2GDSII physical design physical design flow development standard cell libraries

What you'll do

Develop and optimize physical design flows for RTL2GDSII processes.
Utilize industry-standard EDA tools for efficient chip design.
Apply CMOS digital design principles in creating standard cells.
Implement DFT/Scan/LBIST techniques to enhance testability.
Collaborate on the development of advanced physical design methodologies.

What we're looking for

3+ years of professional experience in RTL2GDSII physical design or flow development
Proficiency with industry-standard EDA tools and understanding of their underlying algorithms
Knowledge of CMOS digital design principles, standard cells, and libraries
Basic understanding of DFT/Scan/MBIST/LBIST and their impact on physical design flows
ITAR compliance for U.S. Department of State requirements

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