Physical Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$82,500–$132,000 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Closes
Apr 28, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k
This role $107k
$65k $249k
below market most similar roles pay here above market

This role pays less than 97% of similar roles. Most pay $165,825–$227,350 — the blue band above. At the midpoint, this role pays about $107k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Physical Design Engineer

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JOB TITLE: Physical Design Engineer (New College Grad) The Physical Design Engineer (New College Grad) joins the Physical Design team within the ASIC Products Division. This role involves executing implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. You will perform block-level floorplanning, synthesis, Place and Route flows, clock tree synthesis, timing closure, and signoff across deep sub-micron nodes including N5, N3, N2, and A14. Key responsibilities include performing Static Timing Analysis, debugging timing paths, executing ECOs, and running Physical Verification checks like DRC, LVS, ERC, and Antenna. You will also analyze IR drop and electromigration while developing automated scripts using TCL, Python, Ruby, or Bash. The work addresses complex compute and bandwidth challenges using EDA tools such as Cadence Innovus, Tempus, Synopsys IC Compiler II, and PrimeTime.

What does a Physical Design Engineer earn?

Median $183150 from 38 postings across 9 companies.

See salary data

Skills

ASIC Physical Design Static Timing Analysis (STA) Place and Route (P&R) Clock Tree Synthesis (CTS) Floorplanning Physical Verification DRC LVS ERC IR Drop Electromigration TCL Python Ruby Bash Cadence Innovus Synopsys IC Compiler II DFT UPF CPF FinFET 2.5D/3D Integration CoWoS HBM3/4

What you'll do

  • Execute block-level floorplanning and run placement and route (P&R) flows using industry-standard EDA tools.
  • Perform Static Timing Analysis (STA) to debug timing paths and execute ECOs for timing closure.
  • Run Physical Verification checks including DRC, LVS, ERC, and Antenna to resolve signoff violations.
  • Analyze IR drop and electromigration to ensure power grid integrity.
  • Develop and maintain automated scripts using TCL, Python, or Ruby to enhance flow efficiency.
  • Participate in the physical implementation of high-performance networking, AI/ML accelerators, and custom cloud ASICs.

What we're looking for

  • Bachelor's Degree in Electrical Engineering or Computer Engineering with experience.
  • Master's degree in Electrical Engineering or Computer Engineering with a graduation date within the past 12 months.
  • Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
  • Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
  • Hands-on coursework, lab experience, or academic projects using EDA design tools like Cadence, Synopsys, or Siemens.
  • Proficiency in scripting languages such as TCL, Python, Ruby, or Bash.
  • Legal authorization to work in the U.S.
  • Internship or research experience in ASIC physical design, synthesis, or physical verification (preferred).

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