Physical Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $129,300–$225,300 / yr
Posted: 17 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $177k

$114k most similar roles pay here $277k

This role pays less than 65% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $177k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer, you will join a wide-ranging group focused on high performance PHY design efforts. You will collaborate with architecture, CAD, timing, and logic design teams to manage the physical design process from RTL through final GDSII delivery. Your daily responsibilities include generating block and chip level static timing constraints, building full chip floorplans including pin placement and power grids, and developing low power clock network guidelines. You will perform place and route tasks while implementing ECOs to resolve timing, noise, and EM IR violations. The role requires expertise in physically aware synthesis, extraction, and STA methodology using industry standard tools. You must be proficient in Verilog, Perl, and Tcl scripting to support logic design teams and develop flow for chip integration while resolving LVS and DRC issues.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

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Skills

Physical Design RTL GDSII Floor-planning Place and Route STA Verilog Perl Tcl LVS DRC Synthesis Power Grid Extraction SoC Architecture

What you'll do

Generate block and chip level static timing constraints.
Build full chip floorplans including pin placement, partitions, and power grids.
Develop and validate high performance, low power clock network guidelines.
Perform block level place and route to meet timing, area, and power constraints.
Implement ECOs to fix timing, noise, and EM IR violations.
Run physical design verification flows and provide guidance for LVS/DRC fixes.
Establish CAD and physical design methodologies for correct by construction designs.
Assist in flow development for chip integration.

What we're looking for

Bachelor of Science in Electrical Engineering.
Deep design experience in high PHY and/or SOC designs (preferred).
Deep knowledge of industry standards in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route (preferred).
Experience in developing and implementing Power-grid and Clock specifications (preferred).
Strong understanding of all aspects of Physical construction, Integration, and Physical Verification (preferred).
Knowledge of Basic SoC Architecture and HDL languages like Verilog (preferred).
Power user of industry standard Physical Design & Synthesis tools (preferred).
Deep understanding of scripting languages such as Perl/Tcl, Extraction, and STA methodology (preferred).