Physical Analysis Engineer

What you'll do

• Debug flow-related issues and implement enhancements to the physical design process.
• Perform electrical analyses including Static/Dynamic IR, EM, Noise, and Signal EM at the chip level.
• Execute floor planning and manage clock and power distribution for ASIC physical design.
• Conduct static and dynamic power analysis to verify power gating and clock gating techniques.
• Perform chip-package co-analysis to identify PDN weaknesses and assess impacts on critical timing paths.
• Automate complex engineering workflows using scripting languages like Perl, Tcl, or Python.
• Utilize post-silicon correlation and DFT scan patterns to refine pre-silicon EMIR models and signoff methodologies.
• Drive signoff closure for tape out by managing schedules and multi-functional engineering efforts.

What we're looking for

• Bachelor’s degree or foreign equivalent in Electrical Engineering, Mechatronic Engineering, or a related field.
• Experience designing, simulating, and validating large SOC PDN with complex structures in advanced technology process nodes.
• Experience performing static and power analysis to signoff on power grids using tools like Ansys RedHawk or Cadence Voltus.
• Ability to debug complex EMIR violations and propose effective design fixes.
• Experience conducting static and dynamic power analysis and verifying low power techniques like power gating and clock gating.
• Experience performing chip-package co-analysis to identify PDN weaknesses and assess impacts on critical timing paths.
• Ability to create or automate complex engineering workflows using scripting languages such as Perl, Tcl, or Python.
• Experience utilizing post-silicon correlation and refining pre-silicon EMIR models and signoff methodologies.