Physical Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $150,400–$225,300 / yr
Posted: 1 day ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $188k

$137k most similar roles pay here $274k

This role pays less than 56% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $188k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer, you will join the hardware team to collaborate with package and floorplan teams on pad ring, bump, and RDL designs. You will perform critical physical verification checks including LVS, DRC, design-for-manufacturing, and lithography at both chip and block levels. Your daily responsibilities involve interfacing with CAD and technology teams for flow validation, driving signoff closure during the chip design cycle, and developing best known methods to streamline workflows. You will support partition owners with PnR activities while resolving complex design and flow issues. The role requires expertise in Cadence Virtuoso, Cadence Innovus, and scripting using Tcl, Perl, or Python. You will work on technical challenges involving custom layout routing, automated Place and Route designs, and physical verification analysis to ensure successful tape out for integrated circuits.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

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Skills

DRC LVS Cadence Virtuoso Cadence Innovus Tcl Python Perl CMOS Layout PnR APR RDL Physical Verification tape out

What you'll do

Perform physical verification checks including LVS, DRC, DFM, and lithography at the chip and block levels.
Design custom layout and routing for product and test chips using industry standard tools like Cadence Virtuoso.
Collaborate with package and floorplan teams on pad ring, bump, and RDL designs.
Develop Tcl, Perl, or Python scripts to facilitate the design, verification, and signoff of physical design data.
Drive signoff closure for tape out by collaborating with implementation teams throughout the chip design cycle.
Establish methodologies, guidelines, and checklists to streamline physical design workflows and track progress.
Resolve complex design and flow issues related to physical design and identify technical solutions.
Support partition owners with PnR activities and manage dependencies between top, STA, and block domains.

What we're looking for

Master's degree or foreign equivalent in Electrical Engineering or a related field.
2 years of experience in the job offered or a related occupation.
2 years of experience performing DRC debug using industry standard tools like Calibre.
2 years of experience performing LVS debug using industry standard tools like Calibre.
2 years of experience in CMOS Layout Design using tools such as Cadence Virtuoso.
Experience or education in PNR/APR implementation using tools such as Cadence Innovus.
Experience or education in Tcl, Perl, or Python script development for design and verification.