Principal IC Packaging Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$201,600–$302,400 / yr
Posted
44 days ago
Freshness
Confirmed live yesterday
Closes
Jan 25, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $252k
$135k most similar roles pay here $320k

This role pays more than 88% of similar roles. Most pay $168,200–$226,562 — the shaded band above. At the midpoint, this role pays about $252k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Principal IC Packaging Engineer

The Principal IC Packaging Engineer joins the Packaging Engineering team to lead the development of advanced integrated circuit packaging technologies. This role focuses on spearheading new product introductions for Data Center AI and Power Management markets, driving innovation from initial concept through high-volume manufacturing at assembly suppliers. The engineer will manage multi-disciplinary teams and coordinate with multiple OSAT providers to resolve complex technical challenges. Key responsibilities include overseeing wafer bonding, RDL, 3D, wafer dicing, and 2.5D packaging while ensuring adherence to design rules and reliability standards. Required expertise includes high-density interconnect package design, fan-out bridges, FCBGA, MCM, and wire bond processes. The candidate must possess deep knowledge of materials, equipment, and substrate manufacturing processes to solve technical problems related to high-performance computing products and advanced die-to-die interconnects in a production environment.

What you'll do

  • Lead the development of advanced packaging technologies including wafer bonding, RDL, 3D, and 2.5D packaging.
  • Oversee new product introductions to ensure a smooth transition into high-volume manufacturing at assembly suppliers.
  • Design package architectures that balance performance, reliability, and cost constraints for high-density interconnects.
  • Manage relationships with multiple foundries and OSAT providers to move products from concept to production.
  • Resolve complex technical issues encountered during the development and manufacturing processes.
  • Lead cross-functional teams to manage multiple concurrent programs simultaneously.
  • Apply expertise in packaging materials, equipment, and design rules to ensure manufacturing success.

What we're looking for

  • Bachelor's degree in Chemical, Electrical, or Mechanical Engineering with 8+ years of experience.
  • Master's degree in Chemical, Electrical, or Mechanical Engineering with 7+ years of experience.
  • PhD in Chemical, Electrical, or Mechanical Engineering with 6+ years of experience.
  • Seventeen or more years of hands-on experience in packaging technology development including 2.5D/3D and RDL.
  • Expertise in advanced assembly processes such as wafer bonding, flip chip, wire bond, and SiP.
  • Proficiency in substrate manufacturing processes, design rules, and reliability testing methods.
  • Experience managing relationships with OSAT providers and contract manufacturers for high-volume manufacturing.
  • Proven ability to lead multi-disciplinary teams and manage multiple concurrent technical projects.

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