Senior HSIO Bench Test Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$111,300–$166,900 / yr
Posted
71 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 29, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $175k
This role $139k
$100k most similar roles pay here $217k

This role pays less than 83% of similar roles. Most pay $146,500–$203,225 — the shaded band above. At the midpoint, this role pays about $139k versus about $175k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Senior HSIO Bench Test Engineer

The Senior HSIO Bench Test Engineer joins the Post Silicon Engineering group to develop test solutions for highly integrated SOCs. This role involves defining and executing test methodologies and characterization of High Speed SERDES Interfaces, including PCIe, USB4, UFS, DP, MIPI, and PLLs. The engineer will develop characterization plans to optimize design parameters, validate electrical compliance, and perform first silicon bring up and debug for designs fabricated at external foundries. Key responsibilities include analyzing parametric performance, addressing power integrity and signal integrity issues related to package and board design, and resolving customer issues in time-critical environments. Required skills include experience with Oscilloscopes, TDRs, VNAs, and J-BERT equipment, along with proficiency in Python or C# for test automation. The role requires expertise in VLSI technologies, CMOS circuits, and high-speed signal integrity analysis.

What you'll do

  • Develop and execute test methodologies for high-speed SERDES interfaces including PCIe, USB4, UFS, and MIPI.
  • Create characterization plans to optimize design parameters and validate electrical compliance for high-speed interfaces.
  • Perform first silicon bring-up and debug to qualify designs fabricated at external foundries.
  • Analyze technical data of parametric performance across various operating conditions and configurations.
  • Identify and resolve power integrity (PI) and signal integrity (SI) issues related to package and board design.
  • Resolve customer issues and RMA debug tasks in a time-critical environment.
  • Conduct specialized analyses including feasibility studies, signal integrity, and teardown analyses.

What we're looking for

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field (or Master's with 1+ year experience, or PhD).
  • 5+ years of experience in High Speed Silicon Validation.
  • 3+ years of experience in related areas.
  • Knowledge of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal, and semiconductor physics.
  • Knowledge of high-speed test/characterization including eye diagrams, Receiver JTOL performance, jitter analysis, and signal integrity.
  • Hands-on experience with lab equipment such as Oscilloscopes, TDRs, VNAs, and J-BERT.
  • Experience with Python or C# for test automation.
  • Familiarity with board design concepts (preferred); good ASIC device level characterization skills; system level knowledge (plus).

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