Senior HSIO Bench Test Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$117,800–$176,600 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $176k
This role $147k
$107k $223k
below market most similar roles pay here above market

This role pays less than 73% of similar roles. Most pay $147,200–$205,362 — the blue band above. At the midpoint, this role pays about $147k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Senior HSIO Bench Test Engineer

The Senior HSIO Bench Test Engineer joins the Post Silicon Engineering group to develop test solutions for highly integrated SOCs. This role involves defining and executing test methodologies and characterization for High Speed SERDES Interfaces, including PCIe, USB4, UFS, DP, and MIPI. The engineer will develop characterization plans to optimize design parameters, validate electrical compliance, and drive first silicon bring up and debug for designs fabricated at external foundries. Key responsibilities include performing technical data analysis of parametric performance, assisting with power and signal integrity issues, and conducting feasibility studies. Required skills include knowledge of VLSI technologies, CMOS analog and digital integrated circuits, and semiconductor physics. Candidates must be proficient with lab equipment like Oscilloscopes, TDRs, VNAs, and J-BERT, as well as Python or C# for test automation.

What you'll do

  • Define and execute test methodologies for High Speed SERDES interfaces like PCIe, USB4, and UFS.
  • Develop and execute characterization plans to optimize design parameters and validate electrical compliance.
  • Drive first silicon bring up and debug to qualify designs fabricated at external foundries.
  • Perform technical data analysis of parametric performance over various operating conditions and configurations.
  • Assist in hardware design and debug power integrity and signal integrity issues related to package and board design.
  • Resolve customer issues and RMA debugs in a time-critical environment.
  • Conduct specialized analyses including feasibility studies, signal integrity, and teardown analyses.

What we're looking for

  • Bachelor's degree in Electronics/Electrical/Computer Engineering or related field and 2+ years of Hardware Engineering experience.
  • Master's degree in Electronics/Electrical/Computer Engineering or related field and 1+ year of Hardware Engineering experience (preferred).
  • PhD in Computer Science, Electrical/Electronics Engineering, or Engineering.
  • 5+ years of experience in High Speed Silicon Validation.
  • 3+ years of experience in related areas.
  • Knowledge of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal, and semiconductor physics.
  • Knowledge of High Speed test and characterization including eye diagrams, Receiver JTOL, Jitter analysis, and signal integrity.
  • Hands-on experience with lab equipment such as Oscilloscopes, TDRs/VNAs, and J-BERT.
  • Experience with Python or C# for test automation.
  • Familiarity with Board Design concepts such as schematic reviews and layout best practices (preferred).
  • Good ASIC device level characterization skills; system level knowledge is a plus (preferred).
  • Strong verbal and written communication, organization, and documentation skills.
  • Strong problem solving, debugging, and interpersonal skills.

More like this

Similar roles

Senior Bench Test Engineer, HSIO

Qualcomm

San Diego, CA 26 days ago $117,800–$176,600
High Speed SERDES Silicon Validation Python C# Signal Integrity Power Integrity PCIe USB4 UFS MIPI DRAM VLSI ASIC Oscilloscope J-BERT Mixed-Signal Test Automation Schematic Review
2+ yrs exp

Senior Hardware Test Engineer

Qualcomm

San Diego, CA 40 days ago $131,622–$166,900
ATE DFT System-in-Package SoC Bring-up Debugging Characterization High-Volume Manufacturing RF Digital IC Test Programs Hardware/Software Test

Senior Digital Test Engineer

Qualcomm

San Diego, CA 40 days ago $117,800–$176,600
Python Java C++ Linux DFT DFM VLSI ATE Signal Integrity Machine Learning Embedded SW Oscilloscope Spectrum Analyzer Logic Analyzer Network Analyzer Digital Logic Computer Architecture
2+ yrs exp

Senior Test Engineer

General Dynamics

Cape Canaveral, FL 17 days ago $89,505–$99,295
Linux Robot.Framework Scripting System Verification Configuration Management Root Cause Analysis MIL-STD Cloud Native Artificial Intelligence Blockchain AR/VR Quantum Physics Diagnostic Routines Test Procedures Failure Reports
2+ yrs exp

Senior Test Engineer

Medtronic

Tempe, AZ 7 days ago $103,200–$154,800
LabVIEW TestStand ATE Electrical Schematics Measurement Systems Analysis MSA Gauge R&R Oscilloscope Multimeter Arbitrary Waveform Generator Verification & Validation Statistical Analysis Signal Analysis
4+ yrs exp

Senior Test Engineer

General Dynamics

Bloomington, MN 6 days ago $122,553–$135,957
Artificial Intelligence Blockchain AR/VR Cloud Native Quantum Physics Object-Oriented Programming Scripting Languages Test Engineering System Processes Engineering Development Lifecycle
5+ yrs exp