Integrated Circuit Design Verification Engineer
Snap Inc.
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How this pay compares to similar roles
This role pays less than 67% of similar roles. Most pay $168,500–$211,150 — the shaded band above. At the midpoint, this role pays about $175k versus about $190k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 621 open roles on FindRole.
Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.
Most-posted roles
At a glance
Mixed Signal Design Verification Engineer The Mixed Signal Design Verification Engineer joins the design verification team to verify high-speed mixed-signal IP designs including PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, and sensors. This role involves the complete design verification lifecycle from system-level concept to tape out and post-silicon support. Responsibilities include defining pre-silicon and post-silicon testplans based on design specifications, architecting and developing testbenches using SystemVerilog/UVM, authoring assertions in SVA, and ensuring coverage closure. The candidate will utilize tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, and Jaspergold while employing techniques like low power verification, formal verification, and gate level simulation. Required skills include proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl to solve complex integration challenges for 5G, AI/ML, compute, IOT, and automotive applications.
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