Mixed Signal Design Verification Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
32 days ago
Freshness
Confirmed live yesterday
Closes
Feb 7, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $175k
$126k most similar roles pay here $233k

This role pays less than 67% of similar roles. Most pay $168,500–$211,150 — the shaded band above. At the midpoint, this role pays about $175k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 621 open roles on FindRole.

Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.

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At a glance

TL;DR · Mixed Signal Design Verification Engineer

Mixed Signal Design Verification Engineer The Mixed Signal Design Verification Engineer joins the design verification team to verify high-speed mixed-signal IP designs including PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, and sensors. This role involves the complete design verification lifecycle from system-level concept to tape out and post-silicon support. Responsibilities include defining pre-silicon and post-silicon testplans based on design specifications, architecting and developing testbenches using SystemVerilog/UVM, authoring assertions in SVA, and ensuring coverage closure. The candidate will utilize tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, and Jaspergold while employing techniques like low power verification, formal verification, and gate level simulation. Required skills include proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl to solve complex integration challenges for 5G, AI/ML, compute, IOT, and automotive applications.

What you'll do

  • Define pre-silicon and post-silicon testplans based on design specifications and industry standards.
  • Architect and develop testbenches using SystemVerilog, UVM, and mixed-signal simulation methodologies.
  • Author SVA assertions and develop testcases to ensure coverage closure.
  • Perform low power verification, formal verification, and gate level simulations.
  • Execute PHY level verification and integrate designs into subsystems and SoCs.
  • Provide post-silicon validation support for high-speed mixed-signal IP designs.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design, verification, or validation experience.
  • Master's degree in Science, Engineering, or a related field with 3+ years of ASIC design, verification, or validation experience.
  • PhD in Science, Engineering, or a related field with 2+ years of ASIC design, verification, or validation experience.
  • 6+ years of ASIC design verification or related work experience.
  • Knowledge of HVL methodologies such as SystemVerilog/UVM.
  • Experience using ASIC simulation and formal tools like VCS, Xcellium, Modelsim, or Jaspergold.
  • Experience with low power design verification, formal verification, and gate level simulation (preferred).
  • Knowledge of standard protocols (PCIe, USB, MIPI, LPDDR5/6) and scripting languages like Python or Perl (preferred).

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