Mixed Signal RTL Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 111 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $168,500–$240,550 — the blue band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Mixed Signal RTL Design Engineer

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The Mixed Signal RTL Design Engineer will join the hardware team to specify, design, and assist in the verification and lab bring up of advanced mixed-signal circuits. The primary focus involves RTL coding for blocks specified by the engineer or others, alongside writing detailed design specifications. This role requires close collaboration with system architects, circuit designers, and design verification engineers to ensure bug-free silicon. Key responsibilities include using formal tools like LINT, CDC, and RDC to guarantee RTL quality and working with physical design teams for timing closure. Candidates must possess deep knowledge of Verilog, SystemVerilog, mixed-signal concepts, and algorithm development. Proficiency with front-end tools, synthesis, static timing, DFT, and scripting languages like Perl and Python is also required to solve complex hardware design problems.

Skills

RTL Design Verilog System Verilog LINT CDC RDC Python Perl Synthesis DFT System-Verilog assertions Design Verification Scripting

What you'll do

Write RTL code for blocks in advanced mixed-signal circuits.
Author detailed design specifications for hardware blocks.
Use formal tools like LINT, CDC, and RDC to ensure RTL quality.
Support design verification to ensure bug-free silicon.
Work with the physical design team to achieve timing closure.
Support the lab bring-up of silicon.

What we're looking for

Bachelor's of Science in Electrical Engineering (preferred)
10+ years of relevant experience (preferred)
Deep knowledge of RTL design (preferred)
Deep knowledge of Verilog and System Verilog (preferred)
Good knowledge of mixed signal concepts, algorithm development, and scripting languages like Perl and Python (preferred)
Working experience with physical design teams and front-end tools including simulators, linters, and CDC checkers (preferred)
Good knowledge of synthesis, static timing, DFT, and System-Verilog assertions (preferred)
Good communication and presentation skills (preferred)

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