RTL Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$116,400–$203,000 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $160k
$101k most similar roles pay here $256k

This role pays less than 83% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $160k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · RTL Design Engineer

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The RTL Design Engineer joins the mixed-signal silicon design team to work on sophisticated digital and mixed-signal circuits. This role involves specifying, micro-architecting, and coding digital blocks while integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. Day-to-day responsibilities include performing RTL coding, writing meaningful assertions, debugging code, and participating in lab bring-up by writing test scripts and analyzing data. The position requires proficiency in Verilog, SystemVerilog, and scripting languages like Perl, JSON, and Python. Candidates should possess knowledge of front-end tools, low power design methodologies, synthesis, static timing, DFT, and digital signal processing fundamentals. Additionally, the role utilizes GenAI tools for optimizing code. The work focuses on solving complex challenges in mixed-signal circuit integration and high-speed digital systems within a sophisticated semiconductor environment.

Skills

Verilog SystemVerilog RTL Design Mixed-Signal Digital Logic UPF CDC RDC LEQ DFT Synthesis Python Perl JSON GenAI Low Power Design ECO

What you'll do

  • Specify and micro-architect digital blocks within sophisticated mixed-signal circuits.
  • Write RTL code for specified digital blocks using Verilog or SystemVerilog.
  • Develop meaningful assertions and debug code during the design verification process.
  • Integrate high-performance mixed-signal and analog IPs into high-speed digital circuits.
  • Perform lab bring-up by writing test scripts and analyzing experimental data.
  • Implement low power design methodologies to reduce dynamic and static IC power.
  • Utilize GenAI tools to design, validate, and optimize SystemVerilog RTL code.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • Proven knowledge of RTL design, Verilog and SystemVerilog (preferred).
  • Deep knowledge of front-end tools including Verilog simulators, linters, CDC, RDC, LEQ, and UPF (preferred).
  • Experience with low power design methodologies to reduce dynamic and static IC power (preferred).
  • Knowledge of ECO design flows and methodologies (preferred).
  • Understanding of mixed signal concepts and experience with analog circuit behavioral modeling (preferred).
  • Proven knowledge of synthesis, static timing, DFT, and SystemVerilog assertions (preferred).
  • Knowledge of scripting languages like Perl, JSON, Python, and GenAI tools for RTL optimization (preferred).

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