RTL Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Cary, NC
Posted
15 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $199k
$140k most similar roles pay here $251k

This listing doesn't post a salary. Most similar roles pay $168,500–$229,100.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · RTL Design Engineer

Role Posting Log in to save

The RTL Design Engineer joins the mixed-signal silicon design team to work on sophisticated digital and mixed-signal circuits. This role involves specifying, micro-architecting, and coding digital blocks while integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. Day-to-day responsibilities include performing RTL coding, writing meaningful assertions for verification, debugging code, and supporting lab bring-up by writing test scripts and analyzing data. The position requires expertise in Verilog, SystemVerilog, and front-end tools like linters, CDC, RDC, LEQ, and UPF. Candidates should possess skills in low power design methodologies, ECO flows, synthesis, static timing, and DFT. Additional technical competencies include scripting in Perl, JSON, and Python, utilizing GenAI tools for RTL optimization, and applying digital signal processing fundamentals to solve complex problems within the mixed-signal circuit domain.

Skills

RTL Verilog SystemVerilog Mixed-Signal Digital Logic CDC RDC LEQ UPF Low Power Design ECO Synthesis DFT SystemVerilog Assertions Perl Python JSON GenAI

What you'll do

  • Specify and micro-architect digital blocks within sophisticated mixed-signal circuits.
  • Write RTL code for specified digital blocks using Verilog and SystemVerilog.
  • Develop meaningful assertions and debug code during the design verification process.
  • Integrate high-performance mixed-signal and analog IPs into high-speed digital circuits.
  • Implement low-power design methodologies to reduce dynamic and static IC power.
  • Write test scripts and analyze lab data to support hardware bring-up.
  • Utilize GenAI tools to design, validate, and optimize SystemVerilog RTL code.

What we're looking for

  • Bachelor of Science degree.
  • Minimum of 10 years of relevant industry experience.
  • Proven knowledge of RTL design, Verilog, and SystemVerilog (preferred).
  • Deep knowledge of front-end tools including simulators, linters, CDC, RDC, LEQ, and UPF (preferred).
  • Knowledge of low power design methodologies, ECO flows, synthesis, static timing, and DFT (preferred).
  • Experience with mixed signal concepts, analog circuit behavioral modeling, and digital signal processing fundamentals (preferred).
  • Proficiency in SystemVerilog assertions, scripting languages like Perl or Python, and GenAI tools for RTL optimization (preferred).
  • Strong communication and presentation skills (preferred).

Related searches

More RTL Design Engineer jobs RTL Design Engineer jobs in Cary All jobs at Apple Inc

More like this

Similar roles

RTL Design Engineer

Apple Inc

Melbourne, FL 15 days ago
Verilog SystemVerilog RTL Design Mixed-Signal Digital Logic UPF CDC RDC LEQ Synthesis DFT Python Perl JSON GenAI Low Power Design ECO
10+ yrs exp
Save

RTL Design Engineer

Apple Inc

Melbourne, FL 15 days ago
RTL Verilog SystemVerilog Mixed-Signal Digital Logic Low Power Design Synthesis DFT UPF CDC RDC LEQ Python Perl JSON GenAI ECO
Save

RTL Design Engineer

Apple Inc

Waltham, MA 15 days ago $116,400–$203,000
Verilog SystemVerilog RTL Design Mixed-Signal Digital Logic UPF CDC RDC LEQ DFT Synthesis Python Perl JSON GenAI Low Power Design ECO
Save

RTL Design Engineer

Apple Inc

Austin, TX 15 days ago
Verilog SystemVerilog RTL Design DSP Digital Logic Formal Verification Synthesis Static Timing Analysis DFT Python Perl GenAI Hardware-Software Co-design Low-power Design Pipelining Parallelization Testbenches Assertions
10+ yrs exp
Save

RTL Design Engineer

Apple Inc

Cupertino, CA 15 days ago $184,700–$324,800
Verilog SystemVerilog RTL Design DSP Formal Verification Synthesis Static Timing Analysis DFT Python Perl Low-Power Design Hardware-Software Co-design Lab Bring-up Signal Processing
10+ yrs exp
Save

RTL Design Engineer

Apple Inc

Beaverton, OR 15 days ago
Verilog SystemVerilog RTL Design DSP Formal Verification Synthesis Static Timing Analysis DFT Python Perl Low-Power Design Hardware-Software Co-design GenAI
Save