RTL Design Engineer

Apple Inc

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Work type
On-site
Location
Cary, NC
Posted
17 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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How this pay compares to similar roles

Similar $199k
$141k most similar roles pay here $241k

This listing doesn't post a salary. Most similar roles pay $168,000–$229,100.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · RTL Design Engineer

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The RTL Design Engineer joins the mixed-signal silicon design team to work on sophisticated digital and mixed-signal circuits. This role involves specifying, micro-architecting, and coding digital blocks while integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. Day-to-day responsibilities include performing RTL coding, writing meaningful assertions for verification, debugging code, and supporting lab bring-up through test scripts and data analysis. The candidate will utilize Verilog, SystemVerilog, and scripting languages like Perl, JSON, and Python to develop designs. Technical expertise required includes front-end tools, low power design methodologies, ECO flows, synthesis, static timing, and DFT. Additionally, the role requires knowledge of digital signal processing fundamentals and the use of GenAI tools for optimizing code. The work focuses on solving complex challenges in mixed-signal circuit integration and high-speed digital systems.

Skills

RTL Design Verilog SystemVerilog Mixed-Signal Digital Logic Low Power Design Synthesis DFT UPF CDC RDC LEQ Python Perl JSON GenAI ECO Design Test Scripts

What you'll do

  • Specify and micro-architect digital blocks within sophisticated mixed-signal circuits.
  • Write RTL code for specified digital blocks using Verilog or SystemVerilog.
  • Develop meaningful assertions and debug code during the design verification process.
  • Integrate high-performance mixed-signal and analog IPs into high-speed digital circuits.
  • Implement low-power design methodologies to reduce dynamic and static IC power.
  • Write test scripts and analyze lab data to support hardware bring-up.
  • Utilize GenAI tools to design, validate, and optimize SystemVerilog RTL code.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • Proven knowledge of RTL design, Verilog, and SystemVerilog (preferred).
  • Deep knowledge of front-end tools including simulators, linters, CDC, RDC, LEQ, and UPF (preferred).
  • Knowledge of low power design methodologies to reduce dynamic and static IC power (preferred).
  • Experience with ECO design flows and methodologies (preferred).
  • Understanding of mixed signal concepts and experience with analog circuit behavioral modeling (preferred).
  • Proven knowledge of synthesis, static timing, DFT, and SystemVerilog assertions (preferred).
  • Knowledge of scripting languages like Perl, JSON, or Python; GenAI tools; and DSP fundamentals (preferred).

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