RTL Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$165,800–$292,400 / yr
Posted
17 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $229k
$133k most similar roles pay here $309k

This role pays more than 78% of similar roles. Most pay $168,000–$227,900 — the shaded band above. At the midpoint, this role pays about $229k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · RTL Design Engineer

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The RTL Design Engineer joins the mixed-signal silicon design team to work on sophisticated digital and mixed-signal circuits. This role involves specifying, micro-architecting, and coding digital blocks while integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. Day-to-day responsibilities include performing RTL coding, writing meaningful assertions, debugging code, and participating in design verification. The engineer will also support lab bring-up by writing test scripts and analyzing data. Required technical skills include Verilog, SystemVerilog, and front-end tools like linters, CDC, RDC, LEQ, and UPF. Additional competencies include low power design methodologies, ECO flows, synthesis, static timing, DFT, and scripting in Perl, JSON, or Python. The role also utilizes GenAI tools for code optimization and requires knowledge of digital signal processing fundamentals to solve complex mixed-signal integration challenges.

Skills

RTL Verilog SystemVerilog Digital Logic CDC RDC LEQ UPF Low Power Design ECO Synthesis DFT SystemVerilog Assertions Python Perl JSON GenAI

What you'll do

  • Specify and micro-architect digital blocks within sophisticated mixed-signal circuits.
  • Write RTL code for specified digital blocks using Verilog and SystemVerilog.
  • Develop meaningful assertions and debug code during the design verification process.
  • Integrate high-performance mixed-signal and analog IPs into high-speed digital circuits.
  • Perform lab bring-up by writing test scripts and analyzing experimental data.
  • Implement low power design methodologies to reduce dynamic and static IC power.
  • Utilize GenAI tools to design, validate, and optimize SystemVerilog RTL code.

What we're looking for

  • Bachelor of Science degree.
  • Minimum of 10 years of relevant industry experience.
  • Proven knowledge of RTL design, Verilog, and SystemVerilog (preferred).
  • Deep knowledge of front-end tools including simulators, linters, CDC, RDC, LEQ, and UPF (preferred).
  • Knowledge of low power design methodologies and ECO design flows (preferred).
  • Understanding of mixed signal concepts and analog circuit behavioral modeling (preferred).
  • Knowledge of synthesis, static timing, DFT, and SystemVerilog assertions (preferred).
  • Proficiency in scripting languages like Perl, JSON, or Python; experience with GenAI tools; and DSP fundamentals (preferred).

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