Mixed Signal RTL Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
111 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $255k
$129k $346k
below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $168,500–$240,550 — the blue band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Mixed Signal RTL Design Engineer

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The Mixed Signal RTL Design Engineer will join the hardware team to specify, design, and assist in the verification and lab bring up of advanced mixed-signal circuits on the digital side. The role involves writing detailed design specifications and performing RTL coding for blocks specified by the engineer or other team members. Key responsibilities include collaborating with system architects, circuit designers, and design verification engineers to ensure bug-free silicon. The engineer will utilize front-end tools including Verilog simulators, linters, and clock domain crossing checkers to perform LINT, CDC, and RDC checks. Required technical skills include deep knowledge of RTL design, Verilog, SystemVerilog, and mixed-signal concepts. Additional competencies include algorithm development, physical design timing closure, synthesis, static timing, DFT, and scripting in Perl or Python.

Skills

RTL Design Verilog System Verilog Mixed-Signal LINT CDC RDC Python Perl Synthesis DFT System-Verilog assertions Scripting Physical Design Clock Domain Crossing

What you'll do

  • Write RTL code for advanced mixed-signal circuit blocks.
  • Author detailed design specifications for digital components.
  • Use formal tools like LINT, CDC, and RDC to ensure RTL quality.
  • Support design verification efforts to ensure bug-free silicon.
  • Work with the physical design team to achieve timing closure.
  • Support the laboratory bring-up of silicon.

What we're looking for

  • Bachelor's of Science in Electrical Engineering.
  • 10+ years of relevant experience (preferred).
  • Deep knowledge of RTL design (preferred).
  • Deep knowledge of Verilog and System Verilog (preferred).
  • Good knowledge of mixed signal concepts, algorithm development, and scripting languages like Perl and Python (preferred).
  • Working experience with physical design teams (preferred).
  • Good knowledge of front-end tools, synthesis, static timing, and DFT (preferred).
  • Good knowledge of System-Verilog assertions, checkers, and other design verification techniques (preferred).

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