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Active Keyword: Mixed Signal Design Verification Engineer Remove filter Clear all

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Senior Digital / Mixed-Signal IC Design or Verification Engineer

Broadcom

Mendota Heights, MN +1 5 days ago $109,700–$175,500
Actively hiring Confirmed live 3 days ago Posted this week High trust Below market
UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting
8+ yrs exp
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Mixed Signal Design Verification Engineer

Qualcomm

San Diego, CA 33 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Below market
SystemVerilog UVM SVA VCS Questa JasperGold Python Perl Gate Level Simulation Formal Verification mixed signal simulation PCIe USB MIPI CXL LPDDR5 LPDDR6 Low Power Verification
6+ yrs exp
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