Integrated Circuit Design Verification Engineer

Snap Inc.

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Vancouver, Canada
Salary
$173,000–$259,000 / yr
Posted
69 days ago
Freshness
Confirmed live yesterday
Nearby
14 roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k
This role $216k
$121k most similar roles pay here $274k

This role pays more than 76% of similar roles. Most pay $161,500–$214,000 — the shaded band above. At the midpoint, this role pays about $216k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Snap Inc.

Snap Inc. is a technology and camera company, best known for Snapchat, offering visual communication, augmented reality, and advertising products.

Snap Inc. currently has 76 open roles on FindRole.

Listed pay typically runs $209,000–$313,000 across 58 roles with salary data.

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View all roles at Snap Inc.

At a glance

TL;DR · Integrated Circuit Design Verification Engineer

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The Integrated Circuit Design Verification Engineer joins the Spectacles Team to work within a multi-disciplinary group designing display Integrated Circuits for AR. This role involves collaborating with digital design, analog logic, software, and verification engineers to develop and implement UVM-based and assertion-based testbenches. The engineer will create and execute verification test plans involving functional and code coverage while utilizing the Siemens Questa tool set for verification and debug tasks. Key technical requirements include expertise in SystemVerilog, UVM, and Verilog RTL coding practices. Additionally, the candidate must possess skills in scripting and automation using TCL, Make, Perl, Python, and Shell scripts in a Linux environment. The role specifically addresses the technical challenges of designing integrated circuits for augmented reality hardware, with potential exposure to video systems, MIPI, AMBA, I2C, SPI protocols, and embedded microcontrollers.

Skills

UVM SystemVerilog Siemens Questa Verilog Python TCL Make Perl Linux ASIC Design Verification RTL Design Emulation MIPI AMBA I2C SPI

What you'll do

  • Design display Integrated Circuits for augmented reality applications.
  • Develop and implement UVM-based and assertion-based testbenches.
  • Create and execute verification test plans including functional and code coverage.
  • Perform verification and debug tasks using the Siemens Questa tool set.
  • Specify, configure, and create automation tools for the verification process.
  • Write scripts in TCL, Make, Perl, Python, or Shell within a Linux environment.
  • Manage the entire verification process from initial planning to final sign-off.

What we're looking for

  • Must possess a BSEE, MSEE, or equivalent years of experience.
  • Requires experience in ASIC Design Verification.
  • Must have strong knowledge of UVM and SystemVerilog for advanced verification methodologies.
  • Must have strong knowledge of digital functional simulation and the Siemens Questa tool set.
  • Must possess strong knowledge of Verilog RTL coding practices.
  • Must be proficient in scripting and automation using TCL, Make, Perl, Python, and Shell scripts in a Linux environment.
  • Must have excellent written and verbal English communication skills.
  • Preferred experience includes emulation, RTL design, and familiarity with video/display systems and protocols like MIPI, AMBA, I2C, and SPI.

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