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Memory System Designer and Place and Route Engineer

Broadcom

Austin, TX 5 days ago $109,700–$175,500
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog RTL Physical Design STA DRC EM/IR Synthesis Python Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts
8+ yrs exp

Memory Designer

Qualcomm

San Diego, CA 20 days ago $121,800–$182,600
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting
2+ yrs exp

Memory System Designer and Place and Route Engineer

Broadcom

Mendota Heights-Northland 21 days ago $109,700–$175,500
Actively hiring Confirmed live yesterday High trust Below market
Verilog RTL Python STA DRC LVS EM/IR Synthesis Physical Design Place and Route Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts
8+ yrs exp

Memory Designer

Qualcomm

San Diego, CA 40 days ago $174,400–$261,600
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design SRAM Schematic Capture Layout Planning FinFET CMOS SoC PPA L1/L2 Cache Register File Physical Implementation
6+ yrs exp