IOMMU/Virtualization & Memory Mapping Architect

HP Inc.

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Spring, TXPalo Alto, CA
Salary
$147,050–$230,850 / yr
Posted
88 days ago
Freshness
Confirmed live yesterday
Closes
Dec 12, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $217k
This role $189k
$133k most similar roles pay here $281k

This role pays less than 68% of similar roles. Most pay $185,400–$248,412 — the shaded band above. At the midpoint, this role pays about $189k versus about $217k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 104 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 90 roles with salary data.

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At a glance

TL;DR · IOMMU/Virtualization & Memory Mapping Architect

The IOMMU/Virtualization & Memory Mapping Architect joins the engineering team to ensure compute engines share memory efficiently and securely across heterogeneous systems. This role focuses on system-level memory virtualization, mapping, and isolation to enable performant multi-engine execution for AI workloads. Key responsibilities include architecting IOMMU usage for device memory access, defining address translation strategies across CPU, GPU, and NPU platforms, and optimizing DMA, shared buffers, and coherency models. The candidate will also manage hardware design methodologies, lead part qualification processes, and evaluate emerging technologies to align with technical roadmaps. Required expertise includes computer engineering, electrical engineering, and hardware architecture. Technical skills include FPGA, MATLAB, schematic capture, and simulations. This role solves critical problems in memory isolation for multi-tenant environments while ensuring secure execution within complex AI infrastructure and high-performance computing systems.

What you'll do

  • Architect IOMMU usage for device memory access and isolation across heterogeneous systems.
  • Define memory address translation strategies across CPU, GPU, and NPU architectures.
  • Enable virtualization and hypervisor-based memory steering for AI execution environments.
  • Optimize DMA, shared buffers, and coherency models to ensure efficient multi-engine performance.
  • Ensure security and isolation for multi-tenant and enterprise workloads.
  • Develop organization-wide architectures and methodologies for electrical hardware design across multiple platforms.
  • Identify and evaluate emerging technologies and partnerships to align with technology roadmaps.
  • Lead part qualification processes including product quality plans, equipment inspections, and manufacturing qualifications.

What we're looking for

  • Candidates should possess a four-year or graduate degree in Electrical Engineering or a related field.
  • Candidates should have at least 10 years of experience in electrical design, hardware architecture, or a related field.
  • Expertise in memory design and architecture is required to manage system-level memory virtualization and mapping.
  • Proficiency in computer engineering, computer science, and electronic engineering is required.
  • Experience with IOMMU usage for device memory access, isolation, and multi-tenant security is required.
  • Skills in hardware design, systems design, and FPGA technology are required.
  • Ability to perform debugging, simulations, and schematic capture is required.
  • Proficiency in MATLAB and experience with tools like oscilloscopes are preferred.

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