GPU Driver & Memory Management Architect

HP Inc.

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Spring, TXPalo Alto, CA
Salary: $147,050–$230,850 / yr
Posted: 88 days ago
Freshness: Confirmed live yesterday
Closes: Dec 12, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $223k

This role $189k

$131k most similar roles pay here $295k

This role pays less than 76% of similar roles. Most pay $193,000–$253,625 — the shaded band above. At the midpoint, this role pays about $189k versus about $223k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 104 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 90 roles with salary data.

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At a glance

TL;DR · GPU Driver & Memory Management Architect

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As a GPU Driver & Memory Management Architect, you will join the team to explore and develop GPU and NPU-adjacent driver architectures with deep ownership of memory management. You will be responsible for architecting driver-level memory management including DVMT, shared memory models, and WDDM to enable dynamic memory allocation across CPU, GPU, and NPU systems. Your daily work involves optimizing iGPU performance for AI and graphics hybrid workloads, defining OS-driver contracts for Windows and Linux, and resolving memory-related performance bottlenecks while partnering with IHVs like Intel, AMD, and Qualcomm. You will utilize expertise in computer engineering, hardware architecture, and electronics to solve complex problems regarding efficient shared memory utilization. Required skills include proficiency in MATLAB, FPGA, schematic capture, and systems design to ensure scalable architectures for various PCs and improved AI workload performance.

Skills

GPU NPU WDDM DVMT Windows Linux FPGA MATLAB Hardware Architecture Schematic Capture Simulations Electrical Engineering Computer Engineering Debugging

What you'll do

Architect driver-level memory management including DVMT, shared memory models, and WDDM.
Enable dynamic memory allocation across GPU, CPU, and NPU hardware.
Optimize iGPU performance for hybrid AI and graphics workloads.
Define OS-driver contracts for both Windows and Linux platforms.
Diagnose and resolve complex memory-related performance bottlenecks.
Partner with IHVs like Intel, AMD, and Qualcomm on driver capabilities.
Evaluate new technologies and partnerships to align with the technology roadmap.
Track and report product-related performance metrics to ensure quality standards.

What we're looking for

Candidates should possess a four-year or graduate degree in Electrical Engineering or a related discipline.
Applicants should have at least 10 years of experience in electrical design, hardware architecture, or a related field.
Experience must include GPU and memory management architectures including DVMT, shared memory models, and WDDM.
Candidates must be able to architect driver-level memory management and enable dynamic allocation across CPU, GPU, and NPU.
Proficiency in computer engineering, computer science, and hardware design is required.
Skills in debugging, systems design, and simulation are necessary for resolving performance bottlenecks.
Experience with FPGA, PCB design, schematic capture, and MATLAB is preferred.
Candidates must possess strong communication skills and the ability to lead cross-functional teams.

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