Memory Architect

HP Inc.

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Spring, TXTaipei City, Taiwan
Salary
$147,050–$230,850 / yr
Posted
80 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 20, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $189k
$134k most similar roles pay here $270k

This role pays less than 58% of similar roles. Most pay $172,241–$235,750 — the shaded band above. At the midpoint, this role pays about $189k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 104 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 90 roles with salary data.

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View all roles at HP Inc.

At a glance

TL;DR · Memory Architect

Memory Architect The Memory Architect joins the engineering team to design and optimize memory architectures for AI PC designs. This role involves proposing new memory concepts, performing tradeoff analyses between bandwidth and latency, and modeling workload sensitivity across AI, graphics, and productivity mixes. The architect is responsible for developing organization-wide methodologies, evaluating emerging technologies, and influencing supplier roadmaps like JEDEC. Day-to-day tasks include partnering with silicon, firmware, and OS teams to improve memory placement and performance metrics while leading part qualification processes. Key technical skills required include expertise in hardware architecture, electrical engineering, computer science, and systems design. The role utilizes tools such as MATLAB, oscilloscopes, and simulation software. Candidates must navigate complex problems regarding footprint optimization and electronic hardware development to ensure high-quality product outcomes across multiple platforms within the AI PC domain.

What you'll do

  • Propose and explore new memory concepts including placements and workload optimizations for AI PC designs.
  • Analyze workload sensitivity regarding latency, bandwidth, and cache efficiency to optimize for AI and graphics.
  • Drive footprint optimization against bandwidth and latency tradeoffs for various hardware configurations.
  • Partner with silicon, firmware, and OS teams to define memory architectures and design requirements.
  • Influence supplier and industry roadmaps including JEDEC and other memory vendor partnerships.
  • Develop organization-wide methodologies for electrical hardware design across multiple platforms.
  • Lead part qualification processes including product quality plans and manufacturing process qualifications.
  • Track and report performance metrics for electrical and hardware products against established goals.

What we're looking for

  • A four-year or graduate degree in Electrical Engineering or a related discipline is required.
  • Candidates should have at least 10 years of experience in electrical design, hardware architecture, or a related field.
  • Expertise in memory architectures and designing for AI PC systems is required.
  • Proficiency in computer engineering, electronics, and hardware design is necessary.
  • Skills in simulation, schematic capture, and using tools like MATLAB are required.
  • Experience with FPGA, PCB design, and oscilloscope testing is preferred.
  • Ability to analyze workload sensitivity regarding latency, bandwidth, and cache efficiency is required.
  • Strong communication skills and the ability to lead cross-functional teams are required.

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