Distinguished Technologist, AI Model Performance Architect

HP Inc.

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Spring, TXPalo Alto, CA
Salary
$190,000–$274,000 / yr
Posted
93 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 7, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $231k
This role $232k
$173k most similar roles pay here $291k

This role pays less than 51% of similar roles. Most pay $196,750–$265,625 — the shaded band above. At the midpoint, this role pays about $232k versus about $231k for comparable roles.

Based on 240 similar postings.

Employer

About HP Inc.

HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.

HP Inc. currently has 104 open roles on FindRole.

Listed pay typically runs $130,700–$205,200 across 90 roles with salary data.

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At a glance

TL;DR · Distinguished Technologist, AI Model Performance Architect

The Distinguished Technologist - AI Model Performance Architect joins the engineering team to bridge system memory architecture with AI model behavior through hardware and software co-design. This role focuses on developing optimization strategies for faster model startup, improved inferencing efficiency, and reduced memory requirements by analyzing bandwidth, latency, and compute bottlenecks across CPU, GPU, and NPU platforms. The architect will simulate workload execution, manage resource contention, and align model structures with system architecture while defining long-term roadmaps for electrical hardware design. Key technical competencies include experience in electrical engineering, computer science, FPGA, MATLAB, and systems design. The role addresses the critical challenge of optimizing AI workloads through advanced techniques like caching and KV reuse, requiring expertise in electronics, schematic capture, and physics to solve complex performance issues within the domain of high-performance computing and hardware architecture.

What you'll do

  • Analyze system bandwidth, latency, and compute bottlenecks for AI workloads.
  • Model performance across CPU, GPU, and NPU architectures to identify hardware constraints.
  • Simulate workload execution to evaluate PnP tradeoffs and resource contention.
  • Optimize model execution parameters including initialization time, caching, and KV reuse.
  • Drive HW/SW co-design strategies for memory, caching, and scheduling.
  • Align machine learning model structures with underlying system architectures.
  • Develop technology roadmaps and identify growth opportunities for electrical hardware design.
  • Lead industry-leading research and development to introduce innovative solutions across disciplines.

What we're looking for

  • A four-year or graduate degree in Electrical Engineering or a related discipline is required.
  • Candidates should have at least 12 years of experience in electrical design, hardware architecture, or a related field.
  • Expertise in memory and AI model design is required to bridge system memory with AI behavior.
  • Proficiency in hardware/software co-design for optimizing inference efficiency and reducing memory needs is required.
  • Skills in computer science, electronics, and systems design are necessary for analyzing bandwidth and compute bottlenecks.
  • Experience with FPGA, MATLAB, and simulation tools for modeling performance across CPU, GPU, and NPU platforms is preferred.
  • Ability to develop technology roadmaps and communicate strategy to executive staff and industry partners is required.
  • Strong communication skills and results orientation are needed to lead research and mentor less-experienced staff.

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