Implementation Engineer

What you'll do

• Develop and validate chip power intent using UPF at both RTL and netlist levels.
• Establish and manage logic and physical synthesis flows across various technology nodes.
• Create timing constraints by collaborating with ASIC design and DFT teams.
• Perform Static Timing Analysis (STA) and Logic Equivalency Checks (LEC) on netlists.
• Verify top-level integration of analog blocks and perform formal connectivity checks with RFIC teams.
• Manage the handoff to P&R teams and lead timing sign-off for post-P&R databases.
• Ensure chip compliance with DFM criteria by verifying IR/EM results.
• Develop implementation methodologies while integrating AI-driven flows into the design process.

What we're looking for

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of experience in ASIC implementation including synthesis, STA, and P&R for deep sub-micron nodes (preferably 16nm or smaller).
• Experience leading or solely developing methodology and scripts for physical synthesis.
• Proven track record of taping out chips for high volume production.
• Familiarity with implementing chips featuring multiple power islands and power gating.
• Master's or Ph.D. degree in Electrical or Communications Engineering (preferred).
• 7+ years of experience in ASIC implementation (preferred).
• Export control laws and regulations, candidates.