Senior Physical Design Engineer

Amazon Inc

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$185,200–$250,000 / yr
Posted
58 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $172k
This role $218k
$131k $263k
below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $160,000–$184,300 — the blue band above. At the midpoint, this role pays about $218k versus about $172k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior Physical Design Engineer

Sr. Physical Design Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This role involves driving IO and core block physical implementation through synthesis, floor planning, bus and pin planning, place and route, power and clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO, and sign-off. The engineer will work with RTL and logic designers on architectural feasibility studies, power-performance-area tradeoffs, and developing physical design methodologies using AI flows. Key technical requirements include experience with ASIC implementation, STA, DFT, and P&R for deep sub-micron nodes, as well as UPF flow for low power design. The work focuses on defining modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

What does a Physical Design Engineer earn?

Median $177300 from 31 postings across 9 companies.

See salary data

What you'll do

  • Conduct architectural feasibility studies with RTL designers to explore power-performance-area tradeoffs.
  • Drive physical implementation including synthesis, floor planning, place and route, and timing closure.
  • Perform power/clock distribution, congestion analysis, IR drop analysis, and physical verification.
  • Develop physical design methodologies and integrate AI-driven flows into the design process.
  • Evaluate third-party IP and provide technical recommendations for integration.
  • Execute ECO and sign-off procedures for digital chip SOCs.
  • Integrate RF/Analog/Mixed-signal blocks with digital top flows using UPF for low power design.

What we're looking for

  • Must be a U.S. citizen, national, permanent resident, refugee, or granted asylum.
  • Bachelor's degree in Electrical Engineering or a related field.
  • 7+ years of experience in ASIC implementation, including synthesis, STA, DFT, and P&R for deep sub-micron nodes.
  • Master's degree in Electrical or Communications Engineering or a related field (preferred).
  • 10+ years of experience in ASIC implementation (preferred).
  • Experience integrating RF/Analog/Mixed signal blocks with digital top flows with RFA teams (preferred).
  • Strong exposure to UPF flow for low power design (preferred).
  • Export control laws and regulations, candidates.

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