Senior Physical Design Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$159,200–$215,300 / yr
Posted
13 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $170k
This role $187k
$135k most similar roles pay here $224k

This role pays more than 84% of similar roles. Most pay $152,112–$186,975 — the shaded band above. At the midpoint, this role pays about $187k versus about $170k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 457 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 447 roles with salary data.

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View all roles at Amazon Inc

At a glance

TL;DR · Senior Physical Design Engineer

As a Sr. Physical Design Engineer on the Amazon Leo team, you will contribute to the development of digital chip SOCs for communications via Low Earth Orbit satellites and gateways. You will work with RTL and logic designers to conduct architectural feasibility studies and explore power-performance-area tradeoffs for physical design closure. Your daily responsibilities include driving IO and core block implementation through synthesis, floor planning, bus and pin planning, place and route, power and clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO sign-off. You will also develop physical design methodologies using AI flows and evaluate third-party IP. The role requires expertise in ASIC implementation for deep sub-micron nodes, UPF flow for low power design, and integrating RF, analog, and mixed-signal blocks into digital top flows.

What you'll do

  • Conduct architectural feasibility studies and analyze power-performance-area tradeoffs for physical design closure.
  • Execute full physical implementation including synthesis, floor planning, and bus/pin planning.
  • Perform place and route, power/clock distribution, and congestion analysis.
  • Manage timing closure, IR drop analysis, and physical verification for digital SOCs.
  • Develop new physical design methodologies while integrating AI-driven flows.
  • Evaluate third-party IP and provide technical recommendations for integration.
  • Integrate RF, analog, and mixed-signal blocks into digital top flows using UPF flow.

What we're looking for

  • Bachelor's degree in Electrical Engineering or a related field.
  • Master's degree in Electrical or Communications Engineering or a related field.
  • 7+ years of experience in ASIC implementation including synthesis, STA, DFT, and P&R for deep sub-micron nodes.
  • 10+ years of experience in ASIC implementation.
  • Experience integrating RF/Analog/Mixed signal blocks with digital top flows.
  • Strong exposure to UPF flow for low power design.
  • Experience using managed ML/AI solutions.
  • Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status due to export control laws.

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